diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
index c40e643e9366..b458efd4ad9a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
@@ -215,7 +215,7 @@
 		display-timings {
 			native-mode = <&dsi2lvds0>;
 			dsi2lvds0: timing0 {
-				clock-frequency = <87000000>;
+				clock-frequency = <88208000>;
 				hactive = <1920>;
 				vactive = <720>;
 				hfront-porch = <32>;
@@ -251,7 +251,7 @@
 		display-timings {
 			native-mode = <&dsi2lvds1>;
 			dsi2lvds1: timing0 {
-				clock-frequency = <87000000>;
+				clock-frequency = <88208000>;
 				hactive = <1920>;
 				vactive = <720>;
 				hfront-porch = <32>;
@@ -1916,3 +1916,28 @@
 	rockchip,dp-lane-mux = <0 1 2 3>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru PLL_V0PLL>;
+	assigned-clock-rates = <1152000000>;
+};
+
+&vp0 {
+	assigned-clocks = <&cru DCLK_VOP0_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};
+
+&vp1 {
+	assigned-clocks = <&cru DCLK_VOP1_SRC>;
+	assigned-clock-parents = <&cru PLL_GPLL>;
+};
+
+&vp2 {
+	assigned-clocks = <&cru DCLK_VOP2_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};
+
+&vp3 {
+	assigned-clocks = <&cru DCLK_VOP3>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
index 6087fe954ccd..7ee1d48a6a42 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
@@ -215,7 +215,7 @@
 		display-timings {
 			native-mode = <&dsi2lvds0>;
 			dsi2lvds0: timing0 {
-				clock-frequency = <87000000>;
+				clock-frequency = <88208000>;
 				hactive = <1920>;
 				vactive = <720>;
 				hfront-porch = <32>;
@@ -251,7 +251,7 @@
 		display-timings {
 			native-mode = <&dsi2lvds1>;
 			dsi2lvds1: timing0 {
-				clock-frequency = <87000000>;
+				clock-frequency = <88208000>;
 				hactive = <1920>;
 				vactive = <720>;
 				hfront-porch = <32>;
@@ -1916,3 +1916,28 @@
 	rockchip,dp-lane-mux = <0 1 2 3>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru PLL_V0PLL>;
+	assigned-clock-rates = <1152000000>;
+};
+
+&vp0 {
+	assigned-clocks = <&cru DCLK_VOP0_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};
+
+&vp1 {
+	assigned-clocks = <&cru DCLK_VOP1_SRC>;
+	assigned-clock-parents = <&cru PLL_GPLL>;
+};
+
+&vp2 {
+	assigned-clocks = <&cru DCLK_VOP2_SRC>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};
+
+&vp3 {
+	assigned-clocks = <&cru DCLK_VOP3>;
+	assigned-clock-parents = <&cru PLL_V0PLL>;
+};