diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 56020ab9f60d..2948b4ba01ec 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi new file mode 100644 index 000000000000..708a54b636a6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi @@ -0,0 +1,565 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out3>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam4: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy5 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam5: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out5>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy5_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_csi2_input>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + pinctrl-0 = <&i2c5m3_xfer>; + /* module 77/79 0x1a 78/80 0x36 */ + imx464_2: imx464-2@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + avdd-supply = <&vcc_mipicsi0>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "internal_master"; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_3: imx464-3@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + pinctrl-0 = <&i2c4m3_xfer>; + /* 77/79 0x1a 78/80 0x36 */ + imx464_4: imx464-4@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + avdd-supply = <&vcc_mipicsi1>; + reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out4: endpoint { + remote-endpoint = <&mipi_in_ucam4>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_5: imx464-5@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi1>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out5: endpoint { + remote-endpoint = <&mipi_in_ucam5>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&mipi3_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + +&mipi5_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy5_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in5>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds3 { + status = "okay"; + + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds3_sditf { + status = "okay"; + + port { + mipi3_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds5 { + status = "okay"; + + port { + cif_mipi_in5: endpoint { + remote-endpoint = <&mipi5_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds5_sditf { + status = "okay"; + + port { + mipi5_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_lvds_sditf>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts new file mode 100644 index 000000000000..895f1fdc6dee --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-nvr-demo-v10-cam-4x.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO LP4 V10 Board"; + compatible = "rockchip,rk3588-nvr-demo-v10-ipc-4x", + "rockchip,rk3588-nvr-demo-v10", "rockchip,rk3588"; +}; + +&combphy0_ps { + status = "disabled"; +}; + +&combphy1_ps { + status = "disabled"; +}; + +&combphy2_psu { + status = "disabled"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dp1_in_vp0 { + status = "disabled"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2s5_8ch { + status = "disabled"; +}; + +&pcie2x1l0 { + status = "disabled"; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&rkvdec0 { + status = "disabled"; +}; + +&rkvdec0_mmu { + status = "disabled"; +}; + +&rkvdec1_mmu { + status = "disabled"; +}; + +&rkvdec_core1 { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + +&usbdp_phy1 { + status = "disabled"; +}; + +&usbdrd3_1 { + status = "disabled"; +}; + +&usbdrd_dwc3_1 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&u2phy1 { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&u2phy2 { + status = "disabled"; +}; + +&u2phy2_host { + status = "disabled"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy3_host { + status = "disabled"; +};