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arm64: dts: rockchip: px30: Change armclk rate to 600MHz

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The initial voltage may be too low for 816MHz and it is enough for
600MHz. And as the alternate pll clock of armclk is created when
pmucru driver initialize, so move ARMCLK to pmucru node.

Change-Id: I1f443d55c74e5212a19e42e08b54ec946b4692d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-06-21 18:45:42 +08:00
committed by Tao Huang
parent 403e528a22
commit ba98e189b6
2 changed files with 12 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -989,8 +989,8 @@
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_NPLL>, <&cru ARMCLK>;
assigned-clock-rates = <1188000000>, <816000000>;
assigned-clocks = <&cru PLL_NPLL>;
assigned-clock-rates = <1188000000>;
};
cpu_boost: cpu-boost@ff2b8000 {
@@ -1007,16 +1007,16 @@
assigned-clocks =
<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
<&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>,
<&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>,
<&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>,
<&cru SCLK_GPU>;
<&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
assigned-clock-rates =
<1200000000>, <100000000>,
<26000000>, <200000000>,
<200000000>, <150000000>,
<150000000>, <100000000>,
<200000000>;
<26000000>, <600000000>,
<200000000>, <200000000>,
<150000000>, <150000000>,
<100000000>, <200000000>;
};
usb2phy_grf: syscon@ff2c0000 {

6
arch/arm64/boot/dts/rockchip/rk3326.dtsi
View File

@@ -7,10 +7,8 @@
#include "px30.dtsi"
&cru {
assigned-clocks =
<&cru PLL_NPLL>, <&cru ARMCLK>;
assigned-clock-rates =
<1040000000>, <816000000>;
assigned-clocks = <&cru PLL_NPLL>;
assigned-clock-rates = <1040000000>;
};
&gpu_opp_table {