From ba98e189b68be0fe123deb04ebe669d3948f8f61 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 21 Jun 2018 18:45:42 +0800 Subject: [PATCH] arm64: dts: rockchip: px30: Change armclk rate to 600MHz The initial voltage may be too low for 816MHz and it is enough for 600MHz. And as the alternate pll clock of armclk is created when pmucru driver initialize, so move ARMCLK to pmucru node. Change-Id: I1f443d55c74e5212a19e42e08b54ec946b4692d6 Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/px30.dtsi | 20 ++++++++++---------- arch/arm64/boot/dts/rockchip/rk3326.dtsi | 6 ++---- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 3b64b9e8a202..049e344ec54d 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -989,8 +989,8 @@ #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_NPLL>, <&cru ARMCLK>; - assigned-clock-rates = <1188000000>, <816000000>; + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; }; cpu_boost: cpu-boost@ff2b8000 { @@ -1007,16 +1007,16 @@ assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, - <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, - <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>, - <&cru SCLK_GPU>; + <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = <1200000000>, <100000000>, - <26000000>, <200000000>, - <200000000>, <150000000>, - <150000000>, <100000000>, - <200000000>; + <26000000>, <600000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; usb2phy_grf: syscon@ff2c0000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3326.dtsi b/arch/arm64/boot/dts/rockchip/rk3326.dtsi index e0a59f32aeb2..89661162d4dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326.dtsi @@ -7,10 +7,8 @@ #include "px30.dtsi" &cru { - assigned-clocks = - <&cru PLL_NPLL>, <&cru ARMCLK>; - assigned-clock-rates = - <1040000000>, <816000000>; + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1040000000>; }; &gpu_opp_table {