From bac79d727aea323fcb2493522e0b73eee27255db Mon Sep 17 00:00:00 2001 From: Will McVicker Date: Thu, 25 Aug 2022 23:54:03 +0000 Subject: [PATCH] BACKPORT: FROMGIT: PCI: dwc: Add support for 64-bit MSI target address Since not all devices require a 32-bit MSI address, add support to the PCIe host driver to allow setting the DMA mask to 64-bits if the 32-bit allocation fails. This allows kernels to disable ZONE_DMA32 and bounce buffering (swiotlb) without risking not being able to get a 32-bit address during DMA allocation. Basically, in the slim chance that there are no 32-bit allocations available, the current PCIe host driver will fail to allocate the msi_msg page due to a DMA address overflow (seen in [1]). With this patch, the PCIe host can retry the allocation with a 64-bit DMA mask if the current PCIe device advertises 64-bit support via its MSI capabilities. [1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/ Bug: 241473543 Link: https://lore.kernel.org/r/20220825235404.4132818-3-willmcvicker@google.com Reported-by: kernel test robot Signed-off-by: Will McVicker Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring Acked-by: Jingoo Han Change-Id: I8936717b26f3dec453b0a944b26a0bb891905100 (cherry picked from commit e99d8c5e803b9a9f0b5a84165dad3b8895446147 https://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git pci/dwc) --- .../pci/controller/dwc/pcie-designware-host.c | 19 ++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 110cd9f7f6eb..b73c43f1049d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -373,9 +373,22 @@ int dw_pcie_host_init(struct pcie_port *pp) msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, GFP_KERNEL); if (!msi_vaddr) { - dev_err(dev, "Failed to alloc and map MSI data\n"); - ret = -ENOMEM; - goto err_free_msi; + u16 msi_capabilities; + + /* Retry the allocation with a 64-bit mask if supported. */ + msi_capabilities = dw_pcie_msi_capabilities(pci); + if ((msi_capabilities & PCI_MSI_FLAGS_ENABLE) && + (msi_capabilities & PCI_MSI_FLAGS_64BIT)) { + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), + &pp->msi_data, + GFP_KERNEL); + } + if (!msi_vaddr) { + dev_err(dev, "Failed to alloc and map MSI data\n"); + ret = -ENOMEM; + goto err_free_msi; + } } } } diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d92c8a25094f..161ab9d3f304 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -55,6 +55,14 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci) +{ + u8 offset; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); +} + static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, u8 cap) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5742f3d1d1f1..18fd16d60252 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -283,6 +283,7 @@ struct dw_pcie { u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val);