diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile
index 9e48f2764ed3..77f13cb495c4 100644
--- a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile
@@ -2,6 +2,10 @@
 
 dtbo-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += \
 	blueled_off.dtbo \
+	board_multiio.dtbo \
+	board_multiio_canfd.dtbo \
+	board_multiio_oled.dtbo \
+	board_multiio_shtc1.dtbo \
 	board_stepper.dtbo \
 	dht11.dtbo \
 	display_3_5.dtbo \
@@ -26,6 +30,5 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += \
 	uart0-with-ctsrts.dtbo \
 	uart0.dtbo \
 	uart1.dtbo
-
 targets += $(dtbo-y)
 always-y := $(dtbo-y)
diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio.dts
new file mode 100644
index 000000000000..f8f37d297384
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio.dts
@@ -0,0 +1,136 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			key_pad: key_pad {
+				compatible = "gpio-keys";
+				autorepeat;
+
+				left { /* SW 3 */
+					label = "GPIO Key LEFT";
+					linux,code = <105>;
+					gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+				};
+
+				enter { /* SW 4 */
+					label = "GPIO Key ENTER";
+					linux,code = <28>;
+					gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;
+				};
+
+				right { /* SW 5 */
+					label = "GPIO Key RIGHT";
+					linux,code = <106>;
+					gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
+				};
+
+				up { /* SW 6 */
+					label = "GPIO Key UP";
+					linux,code = <103>;
+					gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
+				};
+
+				down { /* SW 7 */
+					label = "GPIO Key DOWN";
+					linux,code = <108>;
+					gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+				};
+			};
+
+			multiio_fan0: pwm-fan {
+				status = "okay";
+				compatible = "pwm-fan";
+				#cooling-cells = <2>;
+				cooling-min-state = <0>;
+				cooling-max-state = <3>;
+				cooling-levels = <0 128 180 240>;
+				interrupt-parent = <&gpio3>;
+				interrupts = <RK_PC5 IRQ_TYPE_EDGE_FALLING>;
+				pulses-per-revolution = <2>;
+				pwms = <&pwm1 0 40000 0>;
+				rockchip,temp-trips = <
+					50000	1
+					60000	2
+					70000	3
+					>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spi1>;
+
+		__overlay__ {
+			num_chipselect = <1>;
+			cs-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			multiio_spidev: spidev@0 {
+				compatible = "rockchip,spidev";
+				reg = <0>;
+				interrupt-parent = <&gpio2>;
+				interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
+				spi-max-frequency = <100000000>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&pwm1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@4 {
+		target = <&pwm3>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@5 {
+		target = <&uart6>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "not_use_it", "default";
+		};
+	};
+
+	fragment@6 {
+		target = <&i2c3>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			multiio_pcf8563: rtc@51 {
+				status = "okay";
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_canfd.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_canfd.dts
new file mode 100644
index 000000000000..a603a55114de
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_canfd.dts
@@ -0,0 +1,52 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			multiio_canfdclk: multiio_canfdclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <20000000>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spi1>;
+
+		__overlay__ {
+			num_chipselect = <2>;
+			cs-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>,
+				<&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			multiio_canfd: canfd@1 {
+				compatible = "microchip,mcp2517fd";
+				pinctrl-names = "default";
+				pinctrl-0 = <&mcp2515_int_pins>;
+				reg = <1>;
+				clocks = <&multiio_canfdclk>;
+				interrupt-parent = <&gpio0>;
+				interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+				spi-max-frequency = <10000000>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_oled.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_oled.dts
new file mode 100644
index 000000000000..017b30295432
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_oled.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&i2c1>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			multiio_oled: oled@3c {
+				status = "okay";
+				compatible = "sinowealth,sh1106-i2c";
+				reg = <0x3c>;
+				width = <128>;
+				height = <64>;
+				rotate = <180>;
+				prechargep1 = <0x01>;
+				prechargep2 = <0x0f>;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_shtc1.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_shtc1.dts
new file mode 100644
index 000000000000..9bfc191243d2
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/board_multiio_shtc1.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&i2c3>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			multiio_shtc1: shtc1@70 {
+				status = "okay";
+				compatible = "shtc1";
+				reg = <0x70>;
+			};
+		};
+	};
+};