From bb1005b17c7b602b83a08b1ec047f396e655f7b2 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 15 Aug 2018 15:36:16 +0800 Subject: [PATCH] clk: rockchip: px30: Add support to set parent rate for vopl dclk Change-Id: I208471f938b1795273c4f33ac35b82d667a2b312 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 58bc65c72423..9b340f5926cd 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -429,7 +429,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { &px30_dclk_vopb_fracmux, 0), GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(2), 4, GFLAGS), - COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, + COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, PX30_CLKGATE_CON(2), 6, GFLAGS), COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,