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perf_event: aml pmu interrupts routing on g12b [1/1]

Browse Source 
PD#SWPL-3088

Problem:
g12b big-little cluster is different from other SoC with pmu
interrupts and registers.
software modifications must adapt to the difference.

Solution:
modify

Verify:
u200 w400

Change-Id: If9217c1025dff5c17d51790f8c216e31b7d6532b
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>

Conflicts:
	arch/arm/boot/dts/amlogic/mesongxl.dtsi
	arch/arm/boot/dts/amlogic/mesongxl_sei210.dtsi
	arch/arm/boot/dts/amlogic/mesongxm.dtsi
	arch/arm/boot/dts/amlogic/mesontxl.dtsi
	arch/arm/include/asm/perf_event.h
	arch/arm/kernel/perf_event_v7.c
	arch/arm64/boot/dts/amlogic/mesong12a.dtsi
	arch/arm64/boot/dts/amlogic/mesongxl.dtsi
	arch/arm64/boot/dts/amlogic/mesongxl_sei210.dtsi
	arch/arm64/boot/dts/amlogic/mesongxm.dtsi
	arch/arm64/boot/dts/amlogic/mesontxl.dtsi
This commit is contained in:
Hanjie Lin
2018-12-14 19:39:58 +08:00
committed by Dongjin Kim
parent 6d4a452b14
commit bb892368ee
1 changed files with 5 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/boot/dts/amlogic/mesontl1.dtsi
View File

@@ -127,19 +127,14 @@
arm_pmu {
compatible = "arm,cortex-a15-pmu";
/* clusterb-enabled; */
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff634400 0x1000>;
/* addr = base + offset << 2 */
sys_cpu_status0_offset = <0xa0>;
sys_cpu_status0_pmuirq_mask = <0xf>;
reg = <0xff634680 0x4>;
cpumasks = <0xf>;
/* default 10ms */
relax_timer_ns = <10000000>;
relax-timer-ns = <10000000>;
/* default 10000us */
max_wait_cnt = <10000>;
max-wait-cnt = <10000>;
};
gic: interrupt-controller@2c001000 {