From bbf7de5ad91c11118bd3d95b8e5f23569db3b242 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 11 Nov 2020 19:10:27 +0800
Subject: [PATCH] arm64: dts: rockchip: enable pcie20 for rk3568-evb1-ddr4-v10

Change-Id: I7f0e64f70d9efe86399f6f69600de323f24f8e13
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 .../dts/rockchip/rk3568-evb1-ddr4-v10.dts     | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts
index 1aacf285c21f..10fb86fc1f45 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts
@@ -42,6 +42,17 @@
 		vin-supply = <&vcc3v3_sys>;
 	};
 
+	pcie20_3v3: gpio-regulator {
+		compatible = "regulator-gpio";
+		regulator-name = "pcie20_3v3";
+		regulator-min-microvolt = <0100000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0x1>;
+		states = <0100000 0x0
+			  3300000 0x1>;
+	};
+
 	pcie30_avdd0v9: pcie30-avdd0v9 {
 		compatible = "regulator-fixed";
 		regulator-name = "pcie30_avdd0v9";
@@ -97,6 +108,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&combphy2_psq {
+	status = "okay";
+};
+
 &gmac0 {
 	phy-mode = "rgmii";
 	clock_in_out = "output";
@@ -161,6 +176,12 @@
 	status = "okay";
 };
 
+&pcie2x1 {
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&pcie20_3v3>;
+	status = "okay";
+};
+
 &pinctrl {
 	headphone {
 		hp_det: hp-det {