From bc018bea9bcc24edb0e795a6d8b0858d530a8460 Mon Sep 17 00:00:00 2001 From: David Brazdil Date: Wed, 20 Apr 2022 14:43:46 +0100 Subject: [PATCH] ANDROID: KVM: arm64: s2mpu: Allow L1ENTRY_* r/o access Allow read-only access to L1ENTRY_ATTR and L1ENTRY_L2TABLE S2MPU registers. This allows the host to dump the register state for debugging purposes. It is safe because the state of the S2MPU is known to the host anyway. Bug: 190463801 Change-Id: I44b3633dbad3c122ce521c37813dbf2ae690a678 Signed-off-by: David Brazdil (cherry picked from commit e56d9603a633e7320ea1973ec0c4474b4cb7392c) Signed-off-by: Mostafa Saleh Signed-off-by: Quentin Perret --- arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c index 8ff0daeae176..89967f2fefcd 100644 --- a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c +++ b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c @@ -402,6 +402,11 @@ static u32 host_mmio_reg_access_mask(size_t off, bool is_write) return read_only & ALL_VIDS_BITMAP; } + /* Allow reading L1ENTRY registers for debugging. */ + if (off >= REG_NS_L1ENTRY_L2TABLE_ADDR(0, 0) && + off < REG_NS_L1ENTRY_ATTR(NR_VIDS, 0)) + return read_only; + /* Allow EL1 IRQ handler to read fault information. */ masked_off = off & ~REG_NS_FAULT_VID_MASK; if ((masked_off == REG_NS_FAULT_PA_LOW(0)) ||