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rk3188: support uart 48M, use cpll=594M, gpll=768M

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This commit is contained in:
chenxing
2013-06-09 09:23:52 +08:00
parent bbef1aa720
commit bc1da20d65
2 changed files with 20 additions and 4 deletions
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15
arch/arm/mach-rk3188/clock_data.c
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@@ -1318,6 +1318,7 @@ static const struct pll_clk_set gpll_clks[] = {
_PLL_SET_CLKS(300000, 1, 50, 4),
_PLL_SET_CLKS(384000, 2, 128, 4),
_PLL_SET_CLKS(594000, 2, 198, 4),
_PLL_SET_CLKS(768000, 1, 64, 2),
_PLL_SET_CLKS(891000, 8, 594, 2),
_PLL_SET_CLKS(1188000, 2, 99, 1),
_PLL_SET_CLKS(1200000, 1, 50, 1),
@@ -3290,6 +3291,11 @@ static void periph_clk_set_init(void)
hclk_p = aclk_p >> 0;
pclk_p = aclk_p >> 1;
break;
case 768 * MHZ:
aclk_p = ppll_rate >> 2;
hclk_p = aclk_p >> 1;
pclk_p = aclk_p >> 2;
break;
case 891 * MHZ:
aclk_p = ppll_rate / 6;
hclk_p = aclk_p >> 0;
@@ -3326,12 +3332,14 @@ static void cpu_axi_init(void)
hclk_cpu_rate = aclk_cpu_rate >> 1;
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
case 384 * MHZ:
cpu_div_rate = gpll_rate >> 1;
aclk_cpu_rate = cpu_div_rate >> 0;
hclk_cpu_rate = aclk_cpu_rate >> 1;
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
case 594 * MHZ:
cpu_div_rate = gpll_rate >> 1;
aclk_cpu_rate = cpu_div_rate >> 0;
@@ -3339,6 +3347,13 @@ static void cpu_axi_init(void)
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
case 768 * MHZ:
cpu_div_rate = gpll_rate >> 2;
aclk_cpu_rate = cpu_div_rate >> 0;
hclk_cpu_rate = aclk_cpu_rate >> 1;
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
case 891 * MHZ:
cpu_div_rate = gpll_rate / 3;
aclk_cpu_rate = cpu_div_rate >> 0;

9
arch/arm/mach-rk3188/include/mach/board.h
View File

@@ -34,6 +34,7 @@ enum _periph_pll {
periph_pll_297mhz = 297000000,
periph_pll_300mhz = 300000000,
periph_pll_384mhz = 384000000,
periph_pll_768mhz = 768000000,
periph_pll_594mhz = 594000000,
periph_pll_1188mhz = 1188000000, /* for box*/
};
@@ -75,11 +76,11 @@ enum _codec_pll {
#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
//#define codec_pll_default codec_pll_594mhz
//#define periph_pll_default periph_pll_384mhz
#define codec_pll_default codec_pll_594mhz
#define periph_pll_default periph_pll_768mhz
#define codec_pll_default codec_pll_798mhz
#define periph_pll_default periph_pll_594mhz
//#define codec_pll_default codec_pll_798mhz
//#define periph_pll_default periph_pll_594mhz
#endif