From bc4d6b2f941dfc2737e91e88374191c0e8d2d9e7 Mon Sep 17 00:00:00 2001 From: "tao.zeng" Date: Tue, 14 Oct 2014 05:54:01 +0000 Subject: [PATCH] PD #98603(98115): Increase delay to 500us after reset PLL for lock error under high temperature Change-Id: If553552029e9ec7e6ec5a743a6076f692e2a9e0d --- arch/arm/mach-meson8b/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-meson8b/clock.c b/arch/arm/mach-meson8b/clock.c index 4b062afb20c3..1ab9f5a6608a 100755 --- a/arch/arm/mach-meson8b/clock.c +++ b/arch/arm/mach-meson8b/clock.c @@ -1221,7 +1221,7 @@ SETPLL: aml_write_reg32(P_HHI_SYS_PLL_CNTL, cpu_clk_cntl); - udelay_scaled(100, dst / 1000000, 24 /*clk_get_rate_xtal*/); + udelay_scaled(500, dst / 1000000, 24 /*clk_get_rate_xtal*/); cntl = aml_read_reg32(P_HHI_SYS_PLL_CNTL); if((cntl & (1<<31)) == 0){