From 1c4b5ecb7ea190fa3e9f9d6891e6c90b60e04f24 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 23 Feb 2022 08:47:20 +0100 Subject: [PATCH 0001/1268] remove the h8300 architecture Signed-off-by: Christoph Hellwig --- .../clock/renesas,h8300-div-clock.txt | 24 - .../devicetree/bindings/h8300/cpu.txt | 13 - .../renesas,h8300h-intc.txt | 22 - .../interrupt-controller/renesas,h8s-intc.txt | 22 - .../memory-controllers/renesas,h8300-bsc.yaml | 35 -- .../features/core/cBPF-JIT/arch-support.txt | 1 - .../features/core/eBPF-JIT/arch-support.txt | 1 - .../core/generic-idle-thread/arch-support.txt | 1 - .../core/jump-labels/arch-support.txt | 1 - .../core/thread-info-in-task/arch-support.txt | 1 - .../features/core/tracehook/arch-support.txt | 1 - .../features/debug/KASAN/arch-support.txt | 1 - .../debug/debug-vm-pgtable/arch-support.txt | 1 - .../debug/gcov-profile-all/arch-support.txt | 1 - .../features/debug/kcov/arch-support.txt | 1 - .../features/debug/kgdb/arch-support.txt | 1 - .../features/debug/kmemleak/arch-support.txt | 1 - .../debug/kprobes-on-ftrace/arch-support.txt | 1 - .../features/debug/kprobes/arch-support.txt | 1 - .../debug/kretprobes/arch-support.txt | 1 - .../features/debug/optprobes/arch-support.txt | 1 - .../debug/stackprotector/arch-support.txt | 1 - .../features/debug/uprobes/arch-support.txt | 1 - .../debug/user-ret-profiler/arch-support.txt | 1 - .../io/dma-contiguous/arch-support.txt | 1 - .../locking/cmpxchg-local/arch-support.txt | 1 - .../features/locking/lockdep/arch-support.txt | 1 - .../locking/queued-rwlocks/arch-support.txt | 1 - .../locking/queued-spinlocks/arch-support.txt | 1 - .../perf/kprobes-event/arch-support.txt | 1 - .../features/perf/perf-regs/arch-support.txt | 1 - .../perf/perf-stackdump/arch-support.txt | 1 - .../membarrier-sync-core/arch-support.txt | 1 - .../sched/numa-balancing/arch-support.txt | 1 - .../seccomp/seccomp-filter/arch-support.txt | 1 - .../time/arch-tick-broadcast/arch-support.txt | 1 - .../time/clockevents/arch-support.txt | 1 - .../time/context-tracking/arch-support.txt | 1 - .../time/irq-time-acct/arch-support.txt | 1 - .../time/virt-cpuacct/arch-support.txt | 1 - .../features/vm/ELF-ASLR/arch-support.txt | 1 - .../features/vm/PG_uncached/arch-support.txt | 1 - .../features/vm/THP/arch-support.txt | 1 - .../features/vm/TLB/arch-support.txt | 1 - .../features/vm/huge-vmap/arch-support.txt | 1 - .../features/vm/ioremap_prot/arch-support.txt | 1 - .../features/vm/pte_special/arch-support.txt | 1 - MAINTAINERS | 11 - arch/h8300/Kbuild | 5 - arch/h8300/Kconfig | 50 -- arch/h8300/Kconfig.cpu | 99 ---- arch/h8300/Kconfig.debug | 2 - arch/h8300/Makefile | 44 -- arch/h8300/boot/Makefile | 27 -- arch/h8300/boot/compressed/Makefile | 45 -- arch/h8300/boot/compressed/head.S | 49 -- arch/h8300/boot/compressed/misc.c | 76 --- arch/h8300/boot/compressed/vmlinux.lds | 35 -- arch/h8300/boot/compressed/vmlinux.scr | 9 - arch/h8300/boot/dts/Makefile | 6 - arch/h8300/boot/dts/edosk2674.dts | 108 ----- arch/h8300/boot/dts/h8300h_sim.dts | 97 ---- arch/h8300/boot/dts/h8s_sim.dts | 100 ---- arch/h8300/configs/edosk2674_defconfig | 48 -- arch/h8300/configs/h8300h-sim_defconfig | 48 -- arch/h8300/configs/h8s-sim_defconfig | 48 -- arch/h8300/include/asm/Kbuild | 8 - arch/h8300/include/asm/bitops.h | 179 -------- arch/h8300/include/asm/bug.h | 13 - arch/h8300/include/asm/byteorder.h | 7 - arch/h8300/include/asm/cache.h | 12 - arch/h8300/include/asm/elf.h | 102 ---- arch/h8300/include/asm/flat.h | 36 -- arch/h8300/include/asm/hash.h | 54 --- arch/h8300/include/asm/io.h | 67 --- arch/h8300/include/asm/irq.h | 25 - arch/h8300/include/asm/irqflags.h | 97 ---- arch/h8300/include/asm/kgdb.h | 45 -- arch/h8300/include/asm/mmu_context.h | 6 - arch/h8300/include/asm/page.h | 17 - arch/h8300/include/asm/page_offset.h | 2 - arch/h8300/include/asm/pgtable.h | 43 -- arch/h8300/include/asm/processor.h | 127 ----- arch/h8300/include/asm/ptrace.h | 39 -- arch/h8300/include/asm/segment.h | 40 -- arch/h8300/include/asm/signal.h | 23 - arch/h8300/include/asm/smp.h | 1 - arch/h8300/include/asm/string.h | 18 - arch/h8300/include/asm/switch_to.h | 52 --- arch/h8300/include/asm/syscall.h | 43 -- arch/h8300/include/asm/thread_info.h | 105 ----- arch/h8300/include/asm/tlb.h | 7 - arch/h8300/include/asm/traps.h | 41 -- arch/h8300/include/asm/user.h | 75 --- arch/h8300/include/asm/vmalloc.h | 4 - arch/h8300/include/uapi/asm/Kbuild | 2 - arch/h8300/include/uapi/asm/byteorder.h | 7 - arch/h8300/include/uapi/asm/posix_types.h | 13 - arch/h8300/include/uapi/asm/ptrace.h | 43 -- arch/h8300/include/uapi/asm/sigcontext.h | 19 - arch/h8300/include/uapi/asm/signal.h | 92 ---- arch/h8300/include/uapi/asm/unistd.h | 8 - arch/h8300/kernel/.gitignore | 2 - arch/h8300/kernel/Makefile | 22 - arch/h8300/kernel/asm-offsets.c | 70 --- arch/h8300/kernel/entry.S | 434 ------------------ arch/h8300/kernel/h8300_ksyms.c | 35 -- arch/h8300/kernel/head_ram.S | 61 --- arch/h8300/kernel/head_rom.S | 111 ----- arch/h8300/kernel/irq.c | 99 ---- arch/h8300/kernel/kgdb.c | 135 ------ arch/h8300/kernel/module.c | 71 --- arch/h8300/kernel/process.c | 173 ------- arch/h8300/kernel/ptrace.c | 200 -------- arch/h8300/kernel/ptrace_h.c | 256 ----------- arch/h8300/kernel/ptrace_s.c | 44 -- arch/h8300/kernel/setup.c | 213 --------- arch/h8300/kernel/signal.c | 287 ------------ arch/h8300/kernel/sim-console.c | 31 -- arch/h8300/kernel/syscalls.c | 15 - arch/h8300/kernel/traps.c | 156 ------- arch/h8300/kernel/vmlinux.lds.S | 69 --- arch/h8300/lib/Makefile | 9 - arch/h8300/lib/abs.S | 21 - arch/h8300/lib/ashldi3.c | 25 - arch/h8300/lib/ashrdi3.c | 25 - arch/h8300/lib/delay.c | 41 -- arch/h8300/lib/libgcc.h | 78 ---- arch/h8300/lib/lshrdi3.c | 24 - arch/h8300/lib/memcpy.S | 86 ---- arch/h8300/lib/memset.S | 70 --- arch/h8300/lib/moddivsi3.S | 73 --- arch/h8300/lib/modsi3.S | 73 --- arch/h8300/lib/muldi3.c | 45 -- arch/h8300/lib/mulsi3.S | 39 -- arch/h8300/lib/ucmpdi2.c | 18 - arch/h8300/lib/udivsi3.S | 77 ---- arch/h8300/mm/Makefile | 6 - arch/h8300/mm/fault.c | 57 --- arch/h8300/mm/init.c | 101 ---- arch/h8300/mm/memory.c | 53 --- drivers/clk/Makefile | 1 - drivers/clk/h8300/Makefile | 3 - drivers/clk/h8300/clk-div.c | 57 --- drivers/clk/h8300/clk-h8s2678.c | 145 ------ drivers/clocksource/Kconfig | 20 - drivers/clocksource/Makefile | 3 - drivers/clocksource/h8300_timer16.c | 192 -------- drivers/clocksource/h8300_timer8.c | 211 --------- drivers/clocksource/h8300_tpu.c | 158 ------- drivers/irqchip/Kconfig | 11 - drivers/irqchip/Makefile | 2 - drivers/irqchip/irq-renesas-h8300h.c | 94 ---- drivers/irqchip/irq-renesas-h8s.c | 102 ---- drivers/net/ethernet/smsc/Kconfig | 4 +- drivers/net/ethernet/smsc/smc91x.h | 11 - drivers/tty/serial/Kconfig | 5 +- init/Kconfig | 3 +- tools/arch/h8300/include/asm/bitsperlong.h | 15 - tools/arch/h8300/include/uapi/asm/mman.h | 7 - 160 files changed, 5 insertions(+), 6981 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt delete mode 100644 Documentation/devicetree/bindings/h8300/cpu.txt delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt delete mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml delete mode 100644 arch/h8300/Kbuild delete mode 100644 arch/h8300/Kconfig delete mode 100644 arch/h8300/Kconfig.cpu delete mode 100644 arch/h8300/Kconfig.debug delete mode 100644 arch/h8300/Makefile delete mode 100644 arch/h8300/boot/Makefile delete mode 100644 arch/h8300/boot/compressed/Makefile delete mode 100644 arch/h8300/boot/compressed/head.S delete mode 100644 arch/h8300/boot/compressed/misc.c delete mode 100644 arch/h8300/boot/compressed/vmlinux.lds delete mode 100644 arch/h8300/boot/compressed/vmlinux.scr delete mode 100644 arch/h8300/boot/dts/Makefile delete mode 100644 arch/h8300/boot/dts/edosk2674.dts delete mode 100644 arch/h8300/boot/dts/h8300h_sim.dts delete mode 100644 arch/h8300/boot/dts/h8s_sim.dts delete mode 100644 arch/h8300/configs/edosk2674_defconfig delete mode 100644 arch/h8300/configs/h8300h-sim_defconfig delete mode 100644 arch/h8300/configs/h8s-sim_defconfig delete mode 100644 arch/h8300/include/asm/Kbuild delete mode 100644 arch/h8300/include/asm/bitops.h delete mode 100644 arch/h8300/include/asm/bug.h delete mode 100644 arch/h8300/include/asm/byteorder.h delete mode 100644 arch/h8300/include/asm/cache.h delete mode 100644 arch/h8300/include/asm/elf.h delete mode 100644 arch/h8300/include/asm/flat.h delete mode 100644 arch/h8300/include/asm/hash.h delete mode 100644 arch/h8300/include/asm/io.h delete mode 100644 arch/h8300/include/asm/irq.h delete mode 100644 arch/h8300/include/asm/irqflags.h delete mode 100644 arch/h8300/include/asm/kgdb.h delete mode 100644 arch/h8300/include/asm/mmu_context.h delete mode 100644 arch/h8300/include/asm/page.h delete mode 100644 arch/h8300/include/asm/page_offset.h delete mode 100644 arch/h8300/include/asm/pgtable.h delete mode 100644 arch/h8300/include/asm/processor.h delete mode 100644 arch/h8300/include/asm/ptrace.h delete mode 100644 arch/h8300/include/asm/segment.h delete mode 100644 arch/h8300/include/asm/signal.h delete mode 100644 arch/h8300/include/asm/smp.h delete mode 100644 arch/h8300/include/asm/string.h delete mode 100644 arch/h8300/include/asm/switch_to.h delete mode 100644 arch/h8300/include/asm/syscall.h delete mode 100644 arch/h8300/include/asm/thread_info.h delete mode 100644 arch/h8300/include/asm/tlb.h delete mode 100644 arch/h8300/include/asm/traps.h delete mode 100644 arch/h8300/include/asm/user.h delete mode 100644 arch/h8300/include/asm/vmalloc.h delete mode 100644 arch/h8300/include/uapi/asm/Kbuild delete mode 100644 arch/h8300/include/uapi/asm/byteorder.h delete mode 100644 arch/h8300/include/uapi/asm/posix_types.h delete mode 100644 arch/h8300/include/uapi/asm/ptrace.h delete mode 100644 arch/h8300/include/uapi/asm/sigcontext.h delete mode 100644 arch/h8300/include/uapi/asm/signal.h delete mode 100644 arch/h8300/include/uapi/asm/unistd.h delete mode 100644 arch/h8300/kernel/.gitignore delete mode 100644 arch/h8300/kernel/Makefile delete mode 100644 arch/h8300/kernel/asm-offsets.c delete mode 100644 arch/h8300/kernel/entry.S delete mode 100644 arch/h8300/kernel/h8300_ksyms.c delete mode 100644 arch/h8300/kernel/head_ram.S delete mode 100644 arch/h8300/kernel/head_rom.S delete mode 100644 arch/h8300/kernel/irq.c delete mode 100644 arch/h8300/kernel/kgdb.c delete mode 100644 arch/h8300/kernel/module.c delete mode 100644 arch/h8300/kernel/process.c delete mode 100644 arch/h8300/kernel/ptrace.c delete mode 100644 arch/h8300/kernel/ptrace_h.c delete mode 100644 arch/h8300/kernel/ptrace_s.c delete mode 100644 arch/h8300/kernel/setup.c delete mode 100644 arch/h8300/kernel/signal.c delete mode 100644 arch/h8300/kernel/sim-console.c delete mode 100644 arch/h8300/kernel/syscalls.c delete mode 100644 arch/h8300/kernel/traps.c delete mode 100644 arch/h8300/kernel/vmlinux.lds.S delete mode 100644 arch/h8300/lib/Makefile delete mode 100644 arch/h8300/lib/abs.S delete mode 100644 arch/h8300/lib/ashldi3.c delete mode 100644 arch/h8300/lib/ashrdi3.c delete mode 100644 arch/h8300/lib/delay.c delete mode 100644 arch/h8300/lib/libgcc.h delete mode 100644 arch/h8300/lib/lshrdi3.c delete mode 100644 arch/h8300/lib/memcpy.S delete mode 100644 arch/h8300/lib/memset.S delete mode 100644 arch/h8300/lib/moddivsi3.S delete mode 100644 arch/h8300/lib/modsi3.S delete mode 100644 arch/h8300/lib/muldi3.c delete mode 100644 arch/h8300/lib/mulsi3.S delete mode 100644 arch/h8300/lib/ucmpdi2.c delete mode 100644 arch/h8300/lib/udivsi3.S delete mode 100644 arch/h8300/mm/Makefile delete mode 100644 arch/h8300/mm/fault.c delete mode 100644 arch/h8300/mm/init.c delete mode 100644 arch/h8300/mm/memory.c delete mode 100644 drivers/clk/h8300/Makefile delete mode 100644 drivers/clk/h8300/clk-div.c delete mode 100644 drivers/clk/h8300/clk-h8s2678.c delete mode 100644 drivers/clocksource/h8300_timer16.c delete mode 100644 drivers/clocksource/h8300_timer8.c delete mode 100644 drivers/clocksource/h8300_tpu.c delete mode 100644 drivers/irqchip/irq-renesas-h8300h.c delete mode 100644 drivers/irqchip/irq-renesas-h8s.c delete mode 100644 tools/arch/h8300/include/asm/bitsperlong.h delete mode 100644 tools/arch/h8300/include/uapi/asm/mman.h diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt deleted file mode 100644 index 399e0da22348..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas H8/300 divider clock - -Required Properties: - - - compatible: Must be "renesas,h8300-div-clock" - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - reg: Base address and length of the divide rate selector - - - renesas,width: bit width of selector - -Example -------- - - cclk: cclk { - compatible = "renesas,h8300-div-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee01b 2>; - renesas,width = <2>; - }; diff --git a/Documentation/devicetree/bindings/h8300/cpu.txt b/Documentation/devicetree/bindings/h8300/cpu.txt deleted file mode 100644 index 70cd58608f4b..000000000000 --- a/Documentation/devicetree/bindings/h8300/cpu.txt +++ /dev/null @@ -1,13 +0,0 @@ -* H8/300 CPU bindings - -Required properties: - -- compatible: Compatible property value should be "renesas,h8300". -- clock-frequency: Contains the clock frequency for CPU, in Hz. - -Example: - - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <20000000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt deleted file mode 100644 index 56e8d82aff34..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* H8/300H Interrupt controller - -Required properties: - -- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- regs: Base address of interrupt controller registers. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - h8intc: interrupt-controller@fee012 { - compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfee012 7>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt deleted file mode 100644 index faded2b1559b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* H8S Interrupt controller - -Required properties: - -- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- regs: Base address of interrupt controller registers. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - h8intc: interrupt-controller@fffe00 { - compatible = "renesas,h8s-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfffe00 24>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml deleted file mode 100644 index 2b18cef99511..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml +++ /dev/null @@ -1,35 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: H8/300 bus controller - -maintainers: - - Krzysztof Kozlowski - - Yoshinori Sato - -properties: - compatible: - items: - - enum: - - renesas,h8300h-bsc - - renesas,h8s-bsc - - const: renesas,h8300-bsc - - reg: - maxItems: 1 - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - memory-controller@fee01e { - compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; - reg = <0xfee01e 8>; - }; diff --git a/Documentation/features/core/cBPF-JIT/arch-support.txt b/Documentation/features/core/cBPF-JIT/arch-support.txt index e59b5215402d..55b2aca6a2c3 100644 --- a/Documentation/features/core/cBPF-JIT/arch-support.txt +++ b/Documentation/features/core/cBPF-JIT/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | TODO | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/core/eBPF-JIT/arch-support.txt b/Documentation/features/core/eBPF-JIT/arch-support.txt index dcbd8679f514..92b723e897d7 100644 --- a/Documentation/features/core/eBPF-JIT/arch-support.txt +++ b/Documentation/features/core/eBPF-JIT/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt index 4efcba7b5239..c1e69d518f1d 100644 --- a/Documentation/features/core/generic-idle-thread/arch-support.txt +++ b/Documentation/features/core/generic-idle-thread/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | ok | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt index 0c801d1bd2da..968ffd3fa20b 100644 --- a/Documentation/features/core/jump-labels/arch-support.txt +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/core/thread-info-in-task/arch-support.txt b/Documentation/features/core/thread-info-in-task/arch-support.txt index bc74d8beea72..cefb0ed6adca 100644 --- a/Documentation/features/core/thread-info-in-task/arch-support.txt +++ b/Documentation/features/core/thread-info-in-task/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt index af34308fce7f..8e1ad2dc15d8 100644 --- a/Documentation/features/core/tracehook/arch-support.txt +++ b/Documentation/features/core/tracehook/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | ok | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt index c244ac7eee26..72392302c543 100644 --- a/Documentation/features/debug/KASAN/arch-support.txt +++ b/Documentation/features/debug/KASAN/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/debug-vm-pgtable/arch-support.txt b/Documentation/features/debug/debug-vm-pgtable/arch-support.txt index fa83403b4aec..db10ff31805d 100644 --- a/Documentation/features/debug/debug-vm-pgtable/arch-support.txt +++ b/Documentation/features/debug/debug-vm-pgtable/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt index b39c1a5de3f3..8c972103d18c 100644 --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/kcov/arch-support.txt b/Documentation/features/debug/kcov/arch-support.txt index 7e44013cc320..e0412ef3ed7d 100644 --- a/Documentation/features/debug/kcov/arch-support.txt +++ b/Documentation/features/debug/kcov/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt index 2cb0576f9180..2dfd383cbe55 100644 --- a/Documentation/features/debug/kgdb/arch-support.txt +++ b/Documentation/features/debug/kgdb/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | ok | | hexagon: | ok | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/kmemleak/arch-support.txt b/Documentation/features/debug/kmemleak/arch-support.txt index e9ac415f8aec..7408dc258f57 100644 --- a/Documentation/features/debug/kmemleak/arch-support.txt +++ b/Documentation/features/debug/kmemleak/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt index 96156e8802a7..fe707c04794a 100644 --- a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt +++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | TODO | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt index ee95ed61909a..7f4ef559ff60 100644 --- a/Documentation/features/debug/kprobes/arch-support.txt +++ b/Documentation/features/debug/kprobes/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt index 612cb97d47b8..0eace8acbde1 100644 --- a/Documentation/features/debug/kretprobes/arch-support.txt +++ b/Documentation/features/debug/kretprobes/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt index d6ff141a6122..b0cbb80e2138 100644 --- a/Documentation/features/debug/optprobes/arch-support.txt +++ b/Documentation/features/debug/optprobes/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | TODO | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt index ad4de22a71ab..7776884e9d0d 100644 --- a/Documentation/features/debug/stackprotector/arch-support.txt +++ b/Documentation/features/debug/stackprotector/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt index 8bd5548a4485..080257b34ecc 100644 --- a/Documentation/features/debug/uprobes/arch-support.txt +++ b/Documentation/features/debug/uprobes/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt index 2a3fe812a5fa..8da784e2d8d1 100644 --- a/Documentation/features/debug/user-ret-profiler/arch-support.txt +++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | TODO | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt index bece89586efa..6bd6ff52a0bd 100644 --- a/Documentation/features/io/dma-contiguous/arch-support.txt +++ b/Documentation/features/io/dma-contiguous/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt index 52bdda004f5c..307d362622c4 100644 --- a/Documentation/features/locking/cmpxchg-local/arch-support.txt +++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt index a8cd163c8b7e..ada677830246 100644 --- a/Documentation/features/locking/lockdep/arch-support.txt +++ b/Documentation/features/locking/lockdep/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | ok | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt index 8c85949752b3..c000efd4b069 100644 --- a/Documentation/features/locking/queued-rwlocks/arch-support.txt +++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt index 5f4e1b3841af..c4decfc115f5 100644 --- a/Documentation/features/locking/queued-spinlocks/arch-support.txt +++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt index 78f3fe080f0e..b2e45810af06 100644 --- a/Documentation/features/perf/kprobes-event/arch-support.txt +++ b/Documentation/features/perf/kprobes-event/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | ok | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt index 5bf3b1854a1f..86fa79b8e719 100644 --- a/Documentation/features/perf/perf-regs/arch-support.txt +++ b/Documentation/features/perf/perf-regs/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt index d88659bb4fc1..9b76c8206b7f 100644 --- a/Documentation/features/perf/perf-stackdump/arch-support.txt +++ b/Documentation/features/perf/perf-stackdump/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt index 883d33b265d6..4ba3b6308aed 100644 --- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt +++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt @@ -34,7 +34,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt index 9affb7c2c500..54814bbb87b2 100644 --- a/Documentation/features/sched/numa-balancing/arch-support.txt +++ b/Documentation/features/sched/numa-balancing/arch-support.txt @@ -11,7 +11,6 @@ | arm: | .. | | arm64: | ok | | csky: | .. | - | h8300: | .. | | hexagon: | .. | | ia64: | TODO | | m68k: | .. | diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt index 26eec58ab819..e243eaa7696f 100644 --- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt +++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt index 8dcaab070c7b..38f06a18bac3 100644 --- a/Documentation/features/time/arch-tick-broadcast/arch-support.txt +++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt index 9a81cb03b1fd..bf640aaed17b 100644 --- a/Documentation/features/time/clockevents/arch-support.txt +++ b/Documentation/features/time/clockevents/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | ok | - | h8300: | ok | | hexagon: | ok | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt index 4ed116c2ec39..45bf771065b4 100644 --- a/Documentation/features/time/context-tracking/arch-support.txt +++ b/Documentation/features/time/context-tracking/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt index bc30c15557c7..25eac3f7597c 100644 --- a/Documentation/features/time/irq-time-acct/arch-support.txt +++ b/Documentation/features/time/irq-time-acct/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | .. | | m68k: | TODO | diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt index 050de43bbbb9..b71a91066e35 100644 --- a/Documentation/features/time/virt-cpuacct/arch-support.txt +++ b/Documentation/features/time/virt-cpuacct/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | ok | - | h8300: | TODO | | hexagon: | TODO | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt index 2949c99fbb2f..64f387045b38 100644 --- a/Documentation/features/vm/ELF-ASLR/arch-support.txt +++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt index 6cde38458596..334353455540 100644 --- a/Documentation/features/vm/PG_uncached/arch-support.txt +++ b/Documentation/features/vm/PG_uncached/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | TODO | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | ok | | m68k: | TODO | diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt index 7dbd6967b37e..36b5dfb4f8d6 100644 --- a/Documentation/features/vm/THP/arch-support.txt +++ b/Documentation/features/vm/THP/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | .. | - | h8300: | .. | | hexagon: | .. | | ia64: | TODO | | m68k: | .. | diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt index e1c3a4c4d107..7d0de7f173d5 100644 --- a/Documentation/features/vm/TLB/arch-support.txt +++ b/Documentation/features/vm/TLB/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | N/A | | csky: | TODO | - | h8300: | .. | | hexagon: | TODO | | ia64: | TODO | | m68k: | .. | diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt index bc53905a0306..64e8e14e67e0 100644 --- a/Documentation/features/vm/huge-vmap/arch-support.txt +++ b/Documentation/features/vm/huge-vmap/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt index 9a0c8783b84d..6bc7f77ef20d 100644 --- a/Documentation/features/vm/ioremap_prot/arch-support.txt +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt @@ -11,7 +11,6 @@ | arm: | TODO | | arm64: | TODO | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt index 40b969f3a6bb..45463dac131f 100644 --- a/Documentation/features/vm/pte_special/arch-support.txt +++ b/Documentation/features/vm/pte_special/arch-support.txt @@ -11,7 +11,6 @@ | arm: | ok | | arm64: | ok | | csky: | TODO | - | h8300: | TODO | | hexagon: | TODO | | ia64: | TODO | | m68k: | TODO | diff --git a/MAINTAINERS b/MAINTAINERS index 777cd6fa2b3d..412382dfac68 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8395,17 +8395,6 @@ L: linux-efi@vger.kernel.org S: Maintained F: block/partitions/efi.* -H8/300 ARCHITECTURE -M: Yoshinori Sato -L: uclinux-h8-devel@lists.sourceforge.jp (moderated for non-subscribers) -S: Maintained -W: http://uclinux-h8.sourceforge.jp -T: git git://git.sourceforge.jp/gitroot/uclinux-h8/linux.git -F: arch/h8300/ -F: drivers/clk/h8300/ -F: drivers/clocksource/h8300_*.c -F: drivers/irqchip/irq-renesas-h8*.c - HABANALABS PCI DRIVER M: Oded Gabbay S: Supported diff --git a/arch/h8300/Kbuild b/arch/h8300/Kbuild deleted file mode 100644 index e4703f3534cc..000000000000 --- a/arch/h8300/Kbuild +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += kernel/ mm/ boot/dts/ - -# for cleaning -subdir- += boot diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig deleted file mode 100644 index 3e3e0f16f7e0..000000000000 --- a/arch/h8300/Kconfig +++ /dev/null @@ -1,50 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config H8300 - def_bool y - select ARCH_32BIT_OFF_T - select ARCH_HAS_BINFMT_FLAT - select BINFMT_FLAT_ARGVP_ENVP_ON_STACK - select BINFMT_FLAT_OLD_ALWAYS_RAM - select GENERIC_ATOMIC64 - select HAVE_UID16 - select VIRT_TO_BUS - select GENERIC_IRQ_SHOW - select FRAME_POINTER - select GENERIC_CPU_DEVICES - select MODULES_USE_ELF_RELA - select COMMON_CLK - select ARCH_WANT_FRAME_POINTERS - select OF - select OF_IRQ - select OF_EARLY_FLATTREE - select TIMER_OF - select H8300_TMR8 - select HAVE_KERNEL_GZIP - select HAVE_KERNEL_LZO - select HAVE_ARCH_KGDB - select HAVE_ARCH_HASH - select CPU_NO_EFFICIENT_FFS - select SET_FS - select UACCESS_MEMCPY - -config CPU_BIG_ENDIAN - def_bool y - -config GENERIC_HWEIGHT - def_bool y - -config NO_IOPORT_MAP - def_bool y - -config GENERIC_CSUM - def_bool y - -config HZ - int - default 100 - -config NR_CPUS - int - default 1 - -source "arch/h8300/Kconfig.cpu" diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu deleted file mode 100644 index c30baa0499fc..000000000000 --- a/arch/h8300/Kconfig.cpu +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config CPU_H8300H - bool - -config CPU_H8S - bool - -config H83069 - bool - select CPU_H8300H - select H8300_TMR16 - select RENESAS_H8300H_INTC - -config H8S2678 - bool - select CPU_H8S - select H8300_TPU - select RENESAS_H8S_INTC - -config RAMKERNEL - bool - -config ROMKERNEL - bool - -menu "Processor type and features" - -choice -prompt "H8/300 platform" - -config H8300_AE3068 - bool "AE-3068/69" - select H83069 - select RAMKERNEL - help - AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support - More Information. (Japanese Only) - - AE-3068/69 Evaluation Board Support - More Information. - - -config H8300_H8MAX - bool "H8MAX" - select H83069 - select RAMKERNEL - help - H8MAX Evaluation Board Support - More Information. (Japanese Only) - - -config H8300_KANEBEBE - bool "KaneBebe" - select H83069 - select RAMKERNEL - help - KaneBebe Evalition Board Support - More Information. (Japanese Only) - - -config H8300H_SIM - bool "H8/300H GDB Simulator" - select H83069 - select ROMKERNEL - help - GDB Simulator Support - More Information. - - -config H8S_EDOSK2674 - bool "EDOSK-2674" - select H8S2678 - select RAMKERNEL - help - Renesas EDOSK-2674 Evaluation Board Support - More Information. - - - -config H8S_SIM - bool "H8S GDB Simulator" - select H8S2678 - select ROMKERNEL - help - GDB Simulator Support - More Information. - - -endchoice - -config H8300_BUILTIN_DTB - string "Builtin DTB" - default "" - -config OFFSET - hex "Load offset" - default 0 - -endmenu diff --git a/arch/h8300/Kconfig.debug b/arch/h8300/Kconfig.debug deleted file mode 100644 index 295942fe3fd5..000000000000 --- a/arch/h8300/Kconfig.debug +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# dummy file, do not delete diff --git a/arch/h8300/Makefile b/arch/h8300/Makefile deleted file mode 100644 index 807f41e60ee4..000000000000 --- a/arch/h8300/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# arch/h8300/Makefile -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# (C) Copyright 2002-2015 Yoshinori Sato -# - -KBUILD_DEFCONFIG := edosk2674_defconfig - -cflags-$(CONFIG_CPU_H8300H) := -mh -aflags-$(CONFIG_CPU_H8300H) := -mh -Wa,--mach=h8300h -ldflags-$(CONFIG_CPU_H8300H) := -mh8300helf_linux -cflags-$(CONFIG_CPU_H8S) := -ms -aflags-$(CONFIG_CPU_H8S) := -ms -Wa,--mach=h8300s -ldflags-$(CONFIG_CPU_H8S) := -mh8300self_linux - -KBUILD_CFLAGS += $(cflags-y) -KBUILD_CFLAGS += -mint32 -fno-builtin -KBUILD_CFLAGS += -D__linux__ -KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\" -KBUILD_AFLAGS += $(aflags-y) -KBUILD_LDFLAGS += $(ldflags-y) - -CHECKFLAGS += -msize-long - -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := $(call cc-cross-prefix, h8300-unknown-linux- h8300-linux-) -endif - -libs-y += arch/$(ARCH)/lib/ - -boot := arch/h8300/boot - -vmlinux.srec vmlinux.bin zImage uImage.bin: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ - -define archhelp - @echo 'vmlinux.bin - Create raw binary' - @echo 'vmlinux.srec - Create srec binary' - @echo 'zImage - Compressed kernel image' -endef diff --git a/arch/h8300/boot/Makefile b/arch/h8300/boot/Makefile deleted file mode 100644 index 8e62df20ebf9..000000000000 --- a/arch/h8300/boot/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# arch/h8300/boot/Makefile - -targets := vmlinux.srec vmlinux.bin zImage -subdir- := compressed - -OBJCOPYFLAGS_vmlinux.srec := -Osrec -OBJCOPYFLAGS_vmlinux.bin := -Obinary -OBJCOPYFLAGS_zImage := -O binary -R .note -R .comment -R .stab -R .stabstr -S - -UIMAGE_LOADADDR = $(CONFIG_RAMBASE) -UIMAGE_ENTRYADDR = $(shell /bin/bash -c 'printf "0x%08x" \ - $$[$(CONFIG_RAMBASE) + $(CONFIG_OFFSET)]') - -$(obj)/vmlinux.srec $(obj)/vmlinux.bin: vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/zImage: $(obj)/compressed/vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/compressed/vmlinux: FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ - -$(obj)/uImage.bin: $(obj)/vmlinux.bin - $(call if_changed,uimage,none) - -CLEAN_FILES += arch/$(ARCH)/vmlinux.bin arch/$(ARCH)/vmlinux.srec arch/$(ARCH)/uImage.bin diff --git a/arch/h8300/boot/compressed/Makefile b/arch/h8300/boot/compressed/Makefile deleted file mode 100644 index 6ab2fa5ba105..000000000000 --- a/arch/h8300/boot/compressed/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# linux/arch/sh/boot/compressed/Makefile -# -# create a compressed vmlinux image from the original vmlinux -# - -targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o - -OBJECTS = $(obj)/head.o $(obj)/misc.o - -# -# IMAGE_OFFSET is the load offset of the compression loader -# Assign dummy values if these 2 variables are not defined, -# in order to suppress error message. -# -CONFIG_MEMORY_START ?= 0x00400000 -CONFIG_BOOT_LINK_OFFSET ?= 0x00280000 -IMAGE_OFFSET := $(shell printf "0x%08x" $$(($(CONFIG_MEMORY_START)+$(CONFIG_BOOT_LINK_OFFSET)))) - -LIBGCC := $(shell $(CROSS-COMPILE)$(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name 2>/dev/null) -LDFLAGS_vmlinux := -Ttext $(IMAGE_OFFSET) -estartup -T $(obj)/vmlinux.lds \ - --defsym output=$(CONFIG_MEMORY_START) - -$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE - $(call if_changed,ld) - -$(obj)/vmlinux.bin: vmlinux FORCE - $(call if_changed,objcopy) - -suffix-$(CONFIG_KERNEL_GZIP) := gzip -suffix-$(CONFIG_KERNEL_LZO) := lzo -compress-$(CONFIG_KERNEL_GZIP) := gzip -compress-$(CONFIG_KERNEL_LZO) := lzo_with_size - -$(obj)/vmlinux.bin.$(suffix-y): $(obj)/vmlinux.bin FORCE - $(call if_changed,$(compress-y)) - -LDFLAGS_piggy.o := -r --format binary --oformat elf32-h8300-linux -T -OBJCOPYFLAGS := -O binary - -$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE - $(call if_changed,ld) - -CFLAGS_misc.o = -O0 diff --git a/arch/h8300/boot/compressed/head.S b/arch/h8300/boot/compressed/head.S deleted file mode 100644 index 11ef509579cf..000000000000 --- a/arch/h8300/boot/compressed/head.S +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/h8300/boot/compressed/head.S - * - * Copyright (C) 2006 Yoshinori Sato - */ - -#include - - .section .text..startup,"ax" - .global startup -startup: - mov.l #startup, sp - mov.l er0, er4 - mov.l #__sbss, er0 - mov.l #__ebss, er1 - sub.l er0, er1 - shlr er1 - shlr er1 - sub.l er2, er2 -1: - mov.l er2, @er0 - adds #4, er0 - dec.l #1, er1 - bne 1b - jsr @decompress_kernel - mov.l er4, er0 - jmp @output - - .align 9 -fake_headers_as_bzImage: - .word 0 - .ascii "HdrS" ; header signature - .word 0x0202 ; header version number (>= 0x0105) - ; or else old loadlin-1.5 will fail) - .word 0 ; default_switch - .word 0 ; SETUPSEG - .word 0x1000 - .word 0 ; pointing to kernel version string - .byte 0 ; = 0, old one (LILO, Loadlin, - ; 0xTV: T=0 for LILO - ; V = version - .byte 1 ; Load flags bzImage=1 - .word 0x8000 ; size to move, when setup is not - .long 0x100000 ; 0x100000 = default for big kernel - .long 0 ; address of loaded ramdisk image - .long 0 ; its size in bytes - - .end diff --git a/arch/h8300/boot/compressed/misc.c b/arch/h8300/boot/compressed/misc.c deleted file mode 100644 index 8915d8fe2e53..000000000000 --- a/arch/h8300/boot/compressed/misc.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/h8300/boot/compressed/misc.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * - * Adapted for h8300 by Yoshinori Sato 2006 - */ - -#include - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -#undef memset -#undef memcpy -#define memzero(s, n) memset((s), (0), (n)) - -extern int _end; -static unsigned long free_mem_ptr; -static unsigned long free_mem_end_ptr; - -extern char input_data[]; -extern int input_len; -extern char output[]; - -#define HEAP_SIZE 0x10000 - -#ifdef CONFIG_KERNEL_GZIP -#include "../../../../lib/decompress_inflate.c" -#endif - -#ifdef CONFIG_KERNEL_LZO -#include "../../../../lib/decompress_unlzo.c" -#endif - -void *memset(void *s, int c, size_t n) -{ - int i; - char *ss = (char *)s; - - for (i = 0; i < n; i++) - ss[i] = c; - return s; -} - -void *memcpy(void *dest, const void *src, size_t n) -{ - int i; - char *d = (char *)dest, *s = (char *)src; - - for (i = 0; i < n; i++) - d[i] = s[i]; - return dest; -} - -static void error(char *x) -{ - while (1) - ; /* Halt */ -} - -void decompress_kernel(void) -{ - free_mem_ptr = (unsigned long)&_end; - free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; - - __decompress(input_data, input_len, NULL, NULL, output, 0, NULL, error); -} diff --git a/arch/h8300/boot/compressed/vmlinux.lds b/arch/h8300/boot/compressed/vmlinux.lds deleted file mode 100644 index 7f7bb419ce15..000000000000 --- a/arch/h8300/boot/compressed/vmlinux.lds +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -SECTIONS -{ - .text : - { - __stext = . ; - __text = .; - *(.text..startup) - *(.text) - __etext = . ; - } - - .rodata : - { - *(.rodata) - } - . = ALIGN(0x4) ; - .data : - - { - . = ALIGN(0x4) ; - __sdata = . ; - ___data_start = . ; - *(.data.*) - } - . = ALIGN(0x4) ; - .bss : - { - __sbss = . ; - *(.bss*) - . = ALIGN(0x4) ; - __ebss = . ; - } - _end = . ; -} diff --git a/arch/h8300/boot/compressed/vmlinux.scr b/arch/h8300/boot/compressed/vmlinux.scr deleted file mode 100644 index a084903603fe..000000000000 --- a/arch/h8300/boot/compressed/vmlinux.scr +++ /dev/null @@ -1,9 +0,0 @@ -SECTIONS -{ - .data : { - input_len = .; - LONG(input_data_end - input_data) input_data = .; - *(.data) - input_data_end = .; - } -} diff --git a/arch/h8300/boot/dts/Makefile b/arch/h8300/boot/dts/Makefile deleted file mode 100644 index c36bbd1f2592..000000000000 --- a/arch/h8300/boot/dts/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += $(addsuffix .dtb.o, $(CONFIG_H8300_BUILTIN_DTB)) - -dtb-$(CONFIG_H8300H_SIM) := h8300h_sim.dtb -dtb-$(CONFIG_H8S_SIM) := h8s_sim.dtb -dtb-$(CONFIG_H8S_EDOSK2674) := edosk2674.dtb diff --git a/arch/h8300/boot/dts/edosk2674.dts b/arch/h8300/boot/dts/edosk2674.dts deleted file mode 100644 index d1733805ea67..000000000000 --- a/arch/h8300/boot/dts/edosk2674.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -/ { - compatible = "renesas,edosk2674"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&h8intc>; - - chosen { - bootargs = "console=ttySC2,38400"; - stdout-path = &sci2; - }; - aliases { - serial0 = &sci0; - serial1 = &sci1; - serial2 = &sci2; - }; - - xclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - pllclk: pllclk { - compatible = "renesas,h8s2678-pll-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xffff3b 1>, <0xffff45 1>; - }; - core_clk: core_clk { - compatible = "renesas,h8300-div-clock"; - clocks = <&pllclk>; - #clock-cells = <0>; - reg = <0xffff3b 1>; - renesas,width = <3>; - }; - fclk: fclk { - compatible = "fixed-factor-clock"; - clocks = <&core_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - memory@400000 { - device_type = "memory"; - reg = <0x400000 0x800000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <33333333>; - }; - }; - - h8intc: interrupt-controller@fffe00 { - compatible = "renesas,h8s-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfffe00 24>; - }; - - bsc: memory-controller@fffec0 { - compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; - reg = <0xfffec0 24>; - }; - - tpu: timer@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - timer8: timer@ffffb0 { - compatible = "renesas,8bit-timer"; - reg = <0xffffb0 10>; - interrupts = <72 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - sci0: serial@ffff78 { - compatible = "renesas,sci"; - reg = <0xffff78 8>; - interrupts = <88 0>, <89 0>, <90 0>, <91 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - sci1: serial@ffff80 { - compatible = "renesas,sci"; - reg = <0xffff80 8>; - interrupts = <92 0>, <93 0>, <94 0>, <95 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - sci2: serial@ffff88 { - compatible = "renesas,sci"; - reg = <0xffff88 8>; - interrupts = <96 0>, <97 0>, <98 0>, <99 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; -}; diff --git a/arch/h8300/boot/dts/h8300h_sim.dts b/arch/h8300/boot/dts/h8300h_sim.dts deleted file mode 100644 index 595398b9d018..000000000000 --- a/arch/h8300/boot/dts/h8300h_sim.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -/ { - compatible = "gnu,gdbsim"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&h8intc>; - - chosen { - bootargs = "earlyprintk=h8300-sim"; - stdout-path = <&sci0>; - }; - aliases { - serial0 = &sci0; - serial1 = &sci1; - }; - - xclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - clock-output-names = "xtal"; - }; - core_clk: core_clk { - compatible = "renesas,h8300-div-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee01b 2>; - renesas,width = <2>; - }; - fclk: fclk { - compatible = "fixed-factor-clock"; - clocks = <&core_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - memory@400000 { - device_type = "memory"; - reg = <0x400000 0x400000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <20000000>; - }; - }; - - h8intc: interrupt-controller@fee012 { - compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfee012 7>; - }; - - bsc: memory-controller@fee01e { - compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; - reg = <0xfee01e 8>; - }; - - timer8: timer@ffff80 { - compatible = "renesas,8bit-timer"; - reg = <0xffff80 10>; - interrupts = <36 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - timer16: timer@ffff68 { - compatible = "renesas,16bit-timer"; - reg = <0xffff68 8>, <0xffff60 8>; - interrupts = <26 0>; - renesas,channel = <0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - sci0: serial@ffffb0 { - compatible = "renesas,sci"; - reg = <0xffffb0 8>; - interrupts = <52 0>, <53 0>, <54 0>, <55 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - sci1: serial@ffffb8 { - compatible = "renesas,sci"; - reg = <0xffffb8 8>; - interrupts = <56 0>, <57 0>, <58 0>, <59 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; -}; diff --git a/arch/h8300/boot/dts/h8s_sim.dts b/arch/h8300/boot/dts/h8s_sim.dts deleted file mode 100644 index 932cc3c5a81b..000000000000 --- a/arch/h8300/boot/dts/h8s_sim.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -/ { - compatible = "gnu,gdbsim"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&h8intc>; - - chosen { - bootargs = "earlyprintk=h8300-sim"; - stdout-path = <&sci0>; - }; - aliases { - serial0 = &sci0; - serial1 = &sci1; - }; - - xclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - pllclk: pllclk { - compatible = "renesas,h8s2678-pll-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>, <0xfee045 2>; - }; - core_clk: core_clk { - compatible = "renesas,h8300-div-clock"; - clocks = <&pllclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>; - renesas,width = <3>; - }; - fclk: fclk { - compatible = "fixed-factor-clock"; - clocks = <&core_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - memory@400000 { - device_type = "memory"; - reg = <0x400000 0x800000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <33333333>; - }; - }; - - h8intc: interrupt-controller@fffe00 { - compatible = "renesas,h8s-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfffe00 24>; - }; - - bsc: memory-controller@fffec0 { - compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; - reg = <0xfffec0 24>; - }; - - tpu: timer@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - timer8: timer@ffffb0 { - compatible = "renesas,8bit-timer"; - reg = <0xffffb0 10>; - interrupts = <72 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - sci0: serial@ffff78 { - compatible = "renesas,sci"; - reg = <0xffff78 8>; - interrupts = <88 0>, <89 0>, <90 0>, <91 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - sci1: serial@ffff80 { - compatible = "renesas,sci"; - reg = <0xffff80 8>; - interrupts = <92 0>, <93 0>, <94 0>, <95 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; -}; diff --git a/arch/h8300/configs/edosk2674_defconfig b/arch/h8300/configs/edosk2674_defconfig deleted file mode 100644 index 23791dcf6c25..000000000000 --- a/arch/h8300/configs/edosk2674_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_USELIB is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_UID16 is not set -# CONFIG_SYSFS_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -# CONFIG_ADVISE_SYSCALLS is not set -CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLOB=y -# CONFIG_BLOCK is not set -CONFIG_H8S_SIM=y -CONFIG_H8300_BUILTIN_DTB="h8s_sim" -# CONFIG_BINFMT_SCRIPT is not set -CONFIG_BINFMT_FLAT=y -# CONFIG_COREDUMP is not set -# CONFIG_UEVENT_HELPER is not set -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -# CONFIG_ALLOW_DEV_COREDUMP is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_FILE_LOCKING is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -# CONFIG_PROC_FS is not set -# CONFIG_SYSFS is not set -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/h8300/configs/h8300h-sim_defconfig b/arch/h8300/configs/h8300h-sim_defconfig deleted file mode 100644 index 7fc9c2f0acc0..000000000000 --- a/arch/h8300/configs/h8300h-sim_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_USELIB is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_UID16 is not set -# CONFIG_SYSFS_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -# CONFIG_ADVISE_SYSCALLS is not set -CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLOB=y -# CONFIG_BLOCK is not set -CONFIG_H8300H_SIM=y -CONFIG_H8300_BUILTIN_DTB="h8300h_sim" -# CONFIG_BINFMT_SCRIPT is not set -CONFIG_BINFMT_FLAT=y -# CONFIG_COREDUMP is not set -# CONFIG_UEVENT_HELPER is not set -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -# CONFIG_ALLOW_DEV_COREDUMP is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_EARLYCON=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_FILE_LOCKING is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -# CONFIG_PROC_FS is not set -# CONFIG_SYSFS is not set -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/h8300/configs/h8s-sim_defconfig b/arch/h8300/configs/h8s-sim_defconfig deleted file mode 100644 index 23791dcf6c25..000000000000 --- a/arch/h8300/configs/h8s-sim_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_USELIB is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_UID16 is not set -# CONFIG_SYSFS_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_BASE_FULL is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -# CONFIG_ADVISE_SYSCALLS is not set -CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLOB=y -# CONFIG_BLOCK is not set -CONFIG_H8S_SIM=y -CONFIG_H8300_BUILTIN_DTB="h8s_sim" -# CONFIG_BINFMT_SCRIPT is not set -CONFIG_BINFMT_FLAT=y -# CONFIG_COREDUMP is not set -# CONFIG_UEVENT_HELPER is not set -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -# CONFIG_ALLOW_DEV_COREDUMP is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_UNIX98_PTYS is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_FILE_LOCKING is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -# CONFIG_PROC_FS is not set -# CONFIG_SYSFS is not set -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/h8300/include/asm/Kbuild b/arch/h8300/include/asm/Kbuild deleted file mode 100644 index e23139c8fc0d..000000000000 --- a/arch/h8300/include/asm/Kbuild +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -generic-y += asm-offsets.h -generic-y += cmpxchg.h -generic-y += extable.h -generic-y += kvm_para.h -generic-y += mcs_spinlock.h -generic-y += parport.h -generic-y += spinlock.h diff --git a/arch/h8300/include/asm/bitops.h b/arch/h8300/include/asm/bitops.h deleted file mode 100644 index 4489e3d6edd3..000000000000 --- a/arch/h8300/include/asm/bitops.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_BITOPS_H -#define _H8300_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - * Copyright 2002, Yoshinori Sato - */ - -#include - -#include -#include -#include - -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only can be included directly -#endif - -/* - * Function prototypes to keep gcc -Wall happy - */ - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - unsigned long result; - - result = -1; - __asm__("1:\n\t" - "shlr.l %1\n\t" - "adds #1,%0\n\t" - "bcs 1b" - : "=r"(result),"=r"(word) - : "0"(result), "1"(word)); - return result; -} - -#define H8300_GEN_BITOP(FNAME, OP) \ -static inline void FNAME(int nr, volatile unsigned long *addr) \ -{ \ - unsigned char *b_addr; \ - unsigned char bit = nr & 7; \ - \ - b_addr = (unsigned char *)addr + ((nr >> 3) ^ 3); \ - if (__builtin_constant_p(nr)) { \ - __asm__(OP " %1,%0" : "+WU"(*b_addr) : "i"(nr & 7)); \ - } else { \ - __asm__(OP " %s1,%0" : "+WU"(*b_addr) : "r"(bit)); \ - } \ -} - -H8300_GEN_BITOP(set_bit, "bset") -H8300_GEN_BITOP(clear_bit, "bclr") -H8300_GEN_BITOP(change_bit, "bnot") -#define __set_bit(nr, addr) set_bit((nr), (addr)) -#define __clear_bit(nr, addr) clear_bit((nr), (addr)) -#define __change_bit(nr, addr) change_bit((nr), (addr)) - -#undef H8300_GEN_BITOP - -static inline int test_bit(int nr, const volatile unsigned long *addr) -{ - int ret = 0; - unsigned char *b_addr; - unsigned char bit = nr & 7; - - b_addr = (unsigned char *)addr + ((nr >> 3) ^ 3); - if (__builtin_constant_p(nr)) { - __asm__("bld %Z2,%1\n\t" - "rotxl %0\n\t" - : "=r"(ret) - : "WU"(*b_addr), "i"(nr & 7), "0"(ret) : "cc"); - } else { - __asm__("btst %w2,%1\n\t" - "beq 1f\n\t" - "inc.l #1,%0\n" - "1:" - : "=r"(ret) - : "WU"(*b_addr), "r"(bit), "0"(ret) : "cc"); - } - return ret; -} - -#define __test_bit(nr, addr) test_bit(nr, addr) - -#define H8300_GEN_TEST_BITOP(FNNAME, OP) \ -static inline int FNNAME(int nr, void *addr) \ -{ \ - int retval = 0; \ - char ccrsave; \ - unsigned char *b_addr; \ - unsigned char bit = nr & 7; \ - \ - b_addr = (unsigned char *)addr + ((nr >> 3) ^ 3); \ - if (__builtin_constant_p(nr)) { \ - __asm__("stc ccr,%s2\n\t" \ - "orc #0x80,ccr\n\t" \ - "bld %4,%1\n\t" \ - OP " %4,%1\n\t" \ - "rotxl.l %0\n\t" \ - "ldc %s2,ccr" \ - : "=r"(retval), "+WU" (*b_addr), "=&r"(ccrsave) \ - : "0"(retval), "i"(nr & 7) : "cc"); \ - } else { \ - __asm__("stc ccr,%t3\n\t" \ - "orc #0x80,ccr\n\t" \ - "btst %s3,%1\n\t" \ - OP " %s3,%1\n\t" \ - "beq 1f\n\t" \ - "inc.l #1,%0\n\t" \ - "1:\n" \ - "ldc %t3,ccr" \ - : "=r"(retval), "+WU" (*b_addr) \ - : "0" (retval), "r"(bit) : "cc"); \ - } \ - return retval; \ -} \ - \ -static inline int __ ## FNNAME(int nr, void *addr) \ -{ \ - int retval = 0; \ - unsigned char *b_addr; \ - unsigned char bit = nr & 7; \ - \ - b_addr = (unsigned char *)addr + ((nr >> 3) ^ 3); \ - if (__builtin_constant_p(nr)) { \ - __asm__("bld %3,%1\n\t" \ - OP " %3,%1\n\t" \ - "rotxl.l %0\n\t" \ - : "=r"(retval), "+WU"(*b_addr) \ - : "0" (retval), "i"(nr & 7)); \ - } else { \ - __asm__("btst %s3,%1\n\t" \ - OP " %s3,%1\n\t" \ - "beq 1f\n\t" \ - "inc.l #1,%0\n\t" \ - "1:" \ - : "=r"(retval), "+WU"(*b_addr) \ - : "0" (retval), "r"(bit)); \ - } \ - return retval; \ -} - -H8300_GEN_TEST_BITOP(test_and_set_bit, "bset") -H8300_GEN_TEST_BITOP(test_and_clear_bit, "bclr") -H8300_GEN_TEST_BITOP(test_and_change_bit, "bnot") -#undef H8300_GEN_TEST_BITOP - -#include - -static inline unsigned long __ffs(unsigned long word) -{ - unsigned long result; - - result = -1; - __asm__("1:\n\t" - "shlr.l %1\n\t" - "adds #1,%0\n\t" - "bcc 1b" - : "=r" (result),"=r"(word) - : "0"(result), "1"(word)); - return result; -} - -#include -#include -#include -#include -#include - -#endif /* __KERNEL__ */ - -#endif /* _H8300_BITOPS_H */ diff --git a/arch/h8300/include/asm/bug.h b/arch/h8300/include/asm/bug.h deleted file mode 100644 index 00fe5e966bb5..000000000000 --- a/arch/h8300/include/asm/bug.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_BUG_H -#define _H8300_BUG_H - -/* always true */ -#define is_valid_bugaddr(addr) (1) - -#include - -struct pt_regs; -extern void die(const char *str, struct pt_regs *fp, unsigned long err); - -#endif diff --git a/arch/h8300/include/asm/byteorder.h b/arch/h8300/include/asm/byteorder.h deleted file mode 100644 index 6eaa7ad5fc2c..000000000000 --- a/arch/h8300/include/asm/byteorder.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __H8300_BYTEORDER_H__ -#define __H8300_BYTEORDER_H__ - -#include - -#endif diff --git a/arch/h8300/include/asm/cache.h b/arch/h8300/include/asm/cache.h deleted file mode 100644 index 4243eb319acf..000000000000 --- a/arch/h8300/include/asm/cache.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ARCH_H8300_CACHE_H -#define __ARCH_H8300_CACHE_H - -/* bytes per L1 cache line */ -#define L1_CACHE_SHIFT 2 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define __cacheline_aligned -#define ____cacheline_aligned - -#endif diff --git a/arch/h8300/include/asm/elf.h b/arch/h8300/include/asm/elf.h deleted file mode 100644 index 029647cda44c..000000000000 --- a/arch/h8300/include/asm/elf.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_H8300_ELF_H -#define __ASM_H8300_ELF_H - -/* - * ELF register definitions.. - */ - -#include -#include - -typedef unsigned long elf_greg_t; - -#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; -typedef unsigned long elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_H8_300) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2MSB -#define ELF_ARCH EM_H8_300 -#if defined(CONFIG_CPU_H8300H) -#define ELF_CORE_EFLAGS 0x810000 -#endif -#if defined(CONFIG_CPU_H8S) -#define ELF_CORE_EFLAGS 0x820000 -#endif - -#define ELF_PLAT_INIT(_r) do { (_r)->er1 = 0; } while (0) - -#define ELF_EXEC_PAGESIZE 4096 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE 0xD0000000UL - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#define R_H8_NONE 0 -#define R_H8_DIR32 1 -#define R_H8_DIR32_28 2 -#define R_H8_DIR32_24 3 -#define R_H8_DIR32_16 4 -#define R_H8_DIR32U 6 -#define R_H8_DIR32U_28 7 -#define R_H8_DIR32U_24 8 -#define R_H8_DIR32U_20 9 -#define R_H8_DIR32U_16 10 -#define R_H8_DIR24 11 -#define R_H8_DIR24_20 12 -#define R_H8_DIR24_16 13 -#define R_H8_DIR24U 14 -#define R_H8_DIR24U_20 15 -#define R_H8_DIR24U_16 16 -#define R_H8_DIR16 17 -#define R_H8_DIR16U 18 -#define R_H8_DIR16S_32 19 -#define R_H8_DIR16S_28 20 -#define R_H8_DIR16S_24 21 -#define R_H8_DIR16S_20 22 -#define R_H8_DIR16S 23 -#define R_H8_DIR8 24 -#define R_H8_DIR8U 25 -#define R_H8_DIR8Z_32 26 -#define R_H8_DIR8Z_28 27 -#define R_H8_DIR8Z_24 28 -#define R_H8_DIR8Z_20 29 -#define R_H8_DIR8Z_16 30 -#define R_H8_PCREL16 31 -#define R_H8_PCREL8 32 -#define R_H8_BPOS 33 -#define R_H8_PCREL32 34 -#define R_H8_GOT32O 35 -#define R_H8_GOT16O 36 -#define R_H8_DIR16A8 59 -#define R_H8_DIR16R8 60 -#define R_H8_DIR24A8 61 -#define R_H8_DIR24R8 62 -#define R_H8_DIR32A16 63 -#define R_H8_ABS32 65 -#define R_H8_ABS32A16 127 - -#endif diff --git a/arch/h8300/include/asm/flat.h b/arch/h8300/include/asm/flat.h deleted file mode 100644 index 78070f924177..000000000000 --- a/arch/h8300/include/asm/flat.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/h8300/asm/include/flat.h -- uClinux flat-format executables - */ - -#ifndef __H8300_FLAT_H__ -#define __H8300_FLAT_H__ - -#include - -/* - * on the H8 a couple of the relocations have an instruction in the - * top byte. As there can only be 24bits of address space, we just - * always preserve that 8bits at the top, when it isn't an instruction - * is is 0 (davidm@snapgear.com) - */ - -#define flat_get_relocate_addr(rel) (rel & ~0x00000001) -static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags, - u32 *addr) -{ - u32 val = get_unaligned((__force u32 *)rp); - if (!(flags & FLAT_FLAG_GOTPIC)) - val &= 0x00ffffff; - *addr = val; - return 0; -} - -static inline int flat_put_addr_at_rp(u32 __user *rp, u32 addr, u32 rel) -{ - u32 *p = (__force u32 *)rp; - put_unaligned((addr & 0x00ffffff) | (*(char *)p << 24), p); - return 0; -} - -#endif /* __H8300_FLAT_H__ */ diff --git a/arch/h8300/include/asm/hash.h b/arch/h8300/include/asm/hash.h deleted file mode 100644 index 2960b4c9e4ed..000000000000 --- a/arch/h8300/include/asm/hash.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_HASH_H -#define _ASM_HASH_H - -/* - * The later H8SX models have a 32x32-bit multiply, but the H8/300H - * and H8S have only 16x16->32. Since it's tolerably compact, this is - * basically an inlined version of the __mulsi3 code. Since the inputs - * are not expected to be small, it's also simplfied by skipping the - * early-out checks. - * - * (Since neither CPU has any multi-bit shift instructions, a - * shift-and-add version is a non-starter.) - * - * TODO: come up with an arch-specific version of the hashing in fs/namei.c, - * since that is heavily dependent on rotates. Which, as mentioned, suck - * horribly on H8. - */ - -#if defined(CONFIG_CPU_H300H) || defined(CONFIG_CPU_H8S) - -#define HAVE_ARCH__HASH_32 1 - -/* - * Multiply by k = 0x61C88647. Fitting this into three registers requires - * one extra instruction, but reducing register pressure will probably - * make that back and then some. - * - * GCC asm note: %e1 is the high half of operand %1, while %f1 is the - * low half. So if %1 is er4, then %e1 is e4 and %f1 is r4. - * - * This has been designed to modify x in place, since that's the most - * common usage, but preserve k, since hash_64() makes two calls in - * quick succession. - */ -static inline u32 __attribute_const__ __hash_32(u32 x) -{ - u32 temp; - - asm( "mov.w %e1,%f0" - "\n mulxu.w %f2,%0" /* klow * xhigh */ - "\n mov.w %f0,%e1" /* The extra instruction */ - "\n mov.w %f1,%f0" - "\n mulxu.w %e2,%0" /* khigh * xlow */ - "\n add.w %e1,%f0" - "\n mulxu.w %f2,%1" /* klow * xlow */ - "\n add.w %f0,%e1" - : "=&r" (temp), "=r" (x) - : "%r" (GOLDEN_RATIO_32), "1" (x)); - return x; -} - -#endif -#endif /* _ASM_HASH_H */ diff --git a/arch/h8300/include/asm/io.h b/arch/h8300/include/asm/io.h deleted file mode 100644 index 096d99580db6..000000000000 --- a/arch/h8300/include/asm/io.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_IO_H -#define _H8300_IO_H - -#ifdef __KERNEL__ - -#include - -/* H8/300 internal I/O functions */ - -#define __raw_readb __raw_readb -static inline u8 __raw_readb(const volatile void __iomem *addr) -{ - return *(volatile u8 *)addr; -} - -#define __raw_readw __raw_readw -static inline u16 __raw_readw(const volatile void __iomem *addr) -{ - return *(volatile u16 *)addr; -} - -#define __raw_readl __raw_readl -static inline u32 __raw_readl(const volatile void __iomem *addr) -{ - return *(volatile u32 *)addr; -} - -#define __raw_writeb __raw_writeb -static inline void __raw_writeb(u8 b, const volatile void __iomem *addr) -{ - *(volatile u8 *)addr = b; -} - -#define __raw_writew __raw_writew -static inline void __raw_writew(u16 b, const volatile void __iomem *addr) -{ - *(volatile u16 *)addr = b; -} - -#define __raw_writel __raw_writel -static inline void __raw_writel(u32 b, const volatile void __iomem *addr) -{ - *(volatile u32 *)addr = b; -} - -static inline void ctrl_bclr(int b, void __iomem *addr) -{ - if (__builtin_constant_p(b)) - __asm__("bclr %1,%0" : "+WU"(*(u8 *)addr): "i"(b)); - else - __asm__("bclr %w1,%0" : "+WU"(*(u8 *)addr): "r"(b)); -} - -static inline void ctrl_bset(int b, void __iomem *addr) -{ - if (__builtin_constant_p(b)) - __asm__("bset %1,%0" : "+WU"(*(u8 *)addr): "i"(b)); - else - __asm__("bset %w1,%0" : "+WU"(*(u8 *)addr): "r"(b)); -} - -#include - -#endif /* __KERNEL__ */ - -#endif /* _H8300_IO_H */ diff --git a/arch/h8300/include/asm/irq.h b/arch/h8300/include/asm/irq.h deleted file mode 100644 index 776cf06d7a59..000000000000 --- a/arch/h8300/include/asm/irq.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_IRQ_H_ -#define _H8300_IRQ_H_ - -#if defined(CONFIG_CPU_H8300H) -#define NR_IRQS 64 -#define IRQ_CHIP h8300h_irq_chip -#define EXT_IRQ0 12 -#define EXT_IRQS 6 -#elif defined(CONFIG_CPU_H8S) -#define NR_IRQS 128 -#define IRQ_CHIP h8s_irq_chip -#define EXT_IRQ0 16 -#define EXT_IRQS 16 -#endif - -static inline int irq_canonicalize(int irq) -{ - return irq; -} - -void h8300_init_ipr(void); -extern struct irq_chip h8300h_irq_chip; -extern struct irq_chip h8s_irq_chip; -#endif /* _H8300_IRQ_H_ */ diff --git a/arch/h8300/include/asm/irqflags.h b/arch/h8300/include/asm/irqflags.h deleted file mode 100644 index 48756b7f405e..000000000000 --- a/arch/h8300/include/asm/irqflags.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_IRQFLAGS_H -#define _H8300_IRQFLAGS_H - -#ifdef CONFIG_CPU_H8300H -typedef unsigned char h8300flags; - -static inline h8300flags arch_local_save_flags(void) -{ - h8300flags flags; - - __asm__ volatile ("stc ccr,%w0" : "=r" (flags)); - return flags; -} - -static inline void arch_local_irq_disable(void) -{ - __asm__ volatile ("orc #0xc0,ccr"); -} - -static inline void arch_local_irq_enable(void) -{ - __asm__ volatile ("andc #0x3f,ccr"); -} - -static inline h8300flags arch_local_irq_save(void) -{ - h8300flags flags; - - __asm__ volatile ("stc ccr,%w0\n\t" - "orc #0xc0,ccr" : "=r" (flags)); - return flags; -} - -static inline void arch_local_irq_restore(h8300flags flags) -{ - __asm__ volatile ("ldc %w0,ccr" : : "r" (flags) : "cc"); -} - -static inline int arch_irqs_disabled_flags(unsigned long flags) -{ - return (flags & 0xc0) == 0xc0; -} -#endif -#ifdef CONFIG_CPU_H8S -typedef unsigned short h8300flags; - -static inline h8300flags arch_local_save_flags(void) -{ - h8300flags flags; - - __asm__ volatile ("stc ccr,%w0\n\tstc exr,%x0" : "=r" (flags)); - return flags; -} - -static inline void arch_local_irq_disable(void) -{ - __asm__ volatile ("orc #0x80,ccr\n\t"); -} - -static inline void arch_local_irq_enable(void) -{ - __asm__ volatile ("andc #0x7f,ccr\n\t" - "andc #0xf0,exr\n\t"); -} - -static inline h8300flags arch_local_irq_save(void) -{ - h8300flags flags; - - __asm__ volatile ("stc ccr,%w0\n\t" - "stc exr,%x0\n\t" - "orc #0x80,ccr\n\t" - : "=r" (flags)); - return flags; -} - -static inline void arch_local_irq_restore(h8300flags flags) -{ - __asm__ volatile ("ldc %w0,ccr\n\t" - "ldc %x0,exr" - : : "r" (flags) : "cc"); -} - -static inline int arch_irqs_disabled_flags(h8300flags flags) -{ - return (flags & 0x0080) == 0x0080; -} - -#endif - -static inline int arch_irqs_disabled(void) -{ - return arch_irqs_disabled_flags(arch_local_save_flags()); -} - -#endif /* _H8300_IRQFLAGS_H */ diff --git a/arch/h8300/include/asm/kgdb.h b/arch/h8300/include/asm/kgdb.h deleted file mode 100644 index 726ff8fdfc18..000000000000 --- a/arch/h8300/include/asm/kgdb.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2015 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#ifndef _ASM_H8300_KGDB_H -#define _ASM_H8300_KGDB_H - -#define CACHE_FLUSH_IS_SAFE 1 -#define BUFMAX 2048 - -enum regnames { - GDB_ER0, GDB_ER1, GDB_ER2, GDB_ER3, - GDB_ER4, GDB_ER5, GDB_ER6, GDB_SP, - GDB_CCR, GDB_PC, - GDB_CYCLLE, -#if defined(CONFIG_CPU_H8S) - GDB_EXR, -#endif - GDB_TICK, GDB_INST, -#if defined(CONFIG_CPU_H8S) - GDB_MACH, GDB_MACL, -#endif - /* do not change the last entry or anything below! */ - GDB_NUMREGBYTES, /* number of registers */ -}; - -#define GDB_SIZEOF_REG sizeof(u32) -#if defined(CONFIG_CPU_H8300H) -#define DBG_MAX_REG_NUM (13) -#elif defined(CONFIG_CPU_H8S) -#define DBG_MAX_REG_NUM (14) -#endif -#define NUMREGBYTES (DBG_MAX_REG_NUM * GDB_SIZEOF_REG) - -#define BREAK_INSTR_SIZE 2 -static inline void arch_kgdb_breakpoint(void) -{ - __asm__ __volatile__("trapa #2"); -} - -#endif /* _ASM_H8300_KGDB_H */ diff --git a/arch/h8300/include/asm/mmu_context.h b/arch/h8300/include/asm/mmu_context.h deleted file mode 100644 index a9f550f5b5ec..000000000000 --- a/arch/h8300/include/asm/mmu_context.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_H8300_MMU_CONTEXT_H -#define _ASM_H8300_MMU_CONTEXT_H - -#include - -#endif /* _ASM_H8300_MMU_CONTEXT_H */ diff --git a/arch/h8300/include/asm/page.h b/arch/h8300/include/asm/page.h deleted file mode 100644 index 53e037544239..000000000000 --- a/arch/h8300/include/asm/page.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_PAGE_H -#define _H8300_PAGE_H - -#include -#include - -#define MAP_NR(addr) (((uintptr_t)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) - -#ifndef __ASSEMBLY__ -extern unsigned long rom_length; -extern unsigned long memory_start; -extern unsigned long memory_end; -extern unsigned long _ramend; -#endif - -#endif diff --git a/arch/h8300/include/asm/page_offset.h b/arch/h8300/include/asm/page_offset.h deleted file mode 100644 index 888576d7cc2a..000000000000 --- a/arch/h8300/include/asm/page_offset.h +++ /dev/null @@ -1,2 +0,0 @@ - -#define PAGE_OFFSET_RAW 0x00000000 diff --git a/arch/h8300/include/asm/pgtable.h b/arch/h8300/include/asm/pgtable.h deleted file mode 100644 index ea833a5d8bcf..000000000000 --- a/arch/h8300/include/asm/pgtable.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_PGTABLE_H -#define _H8300_PGTABLE_H -#include -extern void paging_init(void); -#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ -#define __swp_type(x) (0) -#define __swp_offset(x) (0) -#define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) -#define kern_addr_valid(addr) (1) -#define pgprot_writecombine(prot) (prot) -#define pgprot_noncached pgprot_writecombine - -static inline int pte_file(pte_t pte) { return 0; } -#define swapper_pg_dir ((pgd_t *) 0) -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -#define ZERO_PAGE(vaddr) (virt_to_page(0)) - -/* - * These would be in other places but having them here reduces the diffs. - */ -extern unsigned int kobjsize(const void *objp); -extern int is_in_rom(unsigned long); - -/* - * All 32bit addresses are effectively valid for vmalloc... - * Sort of meaningless for non-VM targets. - */ -#define VMALLOC_START 0 -#define VMALLOC_END 0xffffffff - -#define arch_enter_lazy_cpu_mode() do {} while (0) - -#endif /* _H8300_PGTABLE_H */ diff --git a/arch/h8300/include/asm/processor.h b/arch/h8300/include/asm/processor.h deleted file mode 100644 index 141a23eb62b7..000000000000 --- a/arch/h8300/include/asm/processor.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-h8300/processor.h - * - * Copyright (C) 2002 Yoshinori Sato - * - * Based on: linux/asm-m68nommu/processor.h - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#ifndef __ASM_H8300_PROCESSOR_H -#define __ASM_H8300_PROCESSOR_H - -#include -#include -#include -#include - -static inline unsigned long rdusp(void) -{ - extern unsigned int _sw_usp; - - return _sw_usp; -} - -static inline void wrusp(unsigned long usp) -{ - extern unsigned int _sw_usp; - - _sw_usp = usp; -} - -/* - * User space process size: 3.75GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ -#define TASK_SIZE (0xFFFFFFFFUL) - -#ifdef __KERNEL__ -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP -#endif - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. We won't be using it - */ -#define TASK_UNMAPPED_BASE 0 - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned long ccr; /* saved status register */ - unsigned long esp0; /* points to SR of stack frame */ - struct { - unsigned short *addr; - unsigned short inst; - } breakinfo; -}; - -#define INIT_THREAD { \ - .ksp = sizeof(init_stack) + (unsigned long)init_stack, \ - .usp = 0, \ - .ccr = PS_S, \ - .esp0 = 0, \ - .breakinfo = { \ - .addr = (unsigned short *)-1, \ - .inst = 0 \ - } \ -} - -/* - * Do necessary setup to start up a newly executed thread. - * - * pass the data segment into user programs if it exists, - * it can't hurt anything as far as I can tell - */ -#if defined(CONFIG_CPU_H8300H) -#define start_thread(_regs, _pc, _usp) \ -do { \ - (_regs)->pc = (_pc); \ - (_regs)->ccr = 0x00; /* clear all flags */ \ - (_regs)->er5 = current->mm->start_data; /* GOT base */ \ - (_regs)->sp = ((unsigned long)(_usp)) - sizeof(unsigned long) * 3; \ -} while (0) -#endif -#if defined(CONFIG_CPU_H8S) -#define start_thread(_regs, _pc, _usp) \ -do { \ - (_regs)->pc = (_pc); \ - (_regs)->ccr = 0x00; /* clear kernel flag */ \ - (_regs)->exr = 0x78; /* enable all interrupts */ \ - (_regs)->er5 = current->mm->start_data; /* GOT base */ \ - /* 14 = space for retaddr(4), vector(4), er0(4) and exr(2) on stack */ \ - (_regs)->sp = ((unsigned long)(_usp)) - 14; \ -} while (0) -#endif - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ -} - -unsigned long __get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) \ - ({ \ - unsigned long eip = 0; \ - if ((tsk)->thread.esp0 > PAGE_SIZE && \ - MAP_NR((tsk)->thread.esp0) < max_mapnr) \ - eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ - eip; }) - -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -#define cpu_relax() barrier() - -#define HARD_RESET_NOW() ({ \ - local_irq_disable(); \ - asm("jmp @@0"); \ -}) - -#endif diff --git a/arch/h8300/include/asm/ptrace.h b/arch/h8300/include/asm/ptrace.h deleted file mode 100644 index 66d383848ff1..000000000000 --- a/arch/h8300/include/asm/ptrace.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_PTRACE_H -#define _H8300_PTRACE_H - -#include - -struct task_struct; - -#ifndef __ASSEMBLY__ -#ifndef PS_S -#define PS_S (0x10) -#endif - -#if defined(CONFIG_CPU_H8300H) -#define H8300_REGS_NO 11 -#endif -#if defined(CONFIG_CPU_H8S) -#define H8300_REGS_NO 12 -#endif - -#define arch_has_single_step() (1) - -#define user_mode(regs) (!((regs)->ccr & PS_S)) -#define instruction_pointer(regs) ((regs)->pc) -#define profile_pc(regs) instruction_pointer(regs) -#define user_stack_pointer(regs) ((regs)->sp) -#define current_pt_regs() ((struct pt_regs *) \ - (THREAD_SIZE + (unsigned long)current_thread_info()) - 1) -#define signal_pt_regs() ((struct pt_regs *)current->thread.esp0) -#define current_user_stack_pointer() rdusp() -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1) - -extern long h8300_get_reg(struct task_struct *task, int regno); -extern int h8300_put_reg(struct task_struct *task, int regno, - unsigned long data); - -#endif /* __ASSEMBLY__ */ -#endif /* _H8300_PTRACE_H */ diff --git a/arch/h8300/include/asm/segment.h b/arch/h8300/include/asm/segment.h deleted file mode 100644 index 37950725d9b9..000000000000 --- a/arch/h8300/include/asm/segment.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_SEGMENT_H -#define _H8300_SEGMENT_H - -/* define constants */ -#define USER_DATA (1) -#ifndef __USER_DS -#define __USER_DS (USER_DATA) -#endif -#define USER_PROGRAM (2) -#define SUPER_DATA (3) -#ifndef __KERNEL_DS -#define __KERNEL_DS (SUPER_DATA) -#endif -#define SUPER_PROGRAM (4) - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -#define USER_DS MAKE_MM_SEG(__USER_DS) -#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) - -/* - * Get/set the SFC/DFC registers for MOVES instructions - */ - -static inline mm_segment_t get_fs(void) -{ - return USER_DS; -} - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#endif /* __ASSEMBLY__ */ - -#endif /* _H8300_SEGMENT_H */ diff --git a/arch/h8300/include/asm/signal.h b/arch/h8300/include/asm/signal.h deleted file mode 100644 index a42f32ca530f..000000000000 --- a/arch/h8300/include/asm/signal.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_SIGNAL_H -#define _H8300_SIGNAL_H - -#include - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define __ARCH_HAS_SA_RESTORER -#include - -#endif /* _H8300_SIGNAL_H */ diff --git a/arch/h8300/include/asm/smp.h b/arch/h8300/include/asm/smp.h deleted file mode 100644 index 9e9bd7e58922..000000000000 --- a/arch/h8300/include/asm/smp.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing required here yet */ diff --git a/arch/h8300/include/asm/string.h b/arch/h8300/include/asm/string.h deleted file mode 100644 index 78e45bb2fef0..000000000000 --- a/arch/h8300/include/asm/string.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_STRING_H_ -#define _H8300_STRING_H_ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#include -#include - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, size_t count); - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *d, const void *s, size_t count); - -#endif /* KERNEL */ - -#endif diff --git a/arch/h8300/include/asm/switch_to.h b/arch/h8300/include/asm/switch_to.h deleted file mode 100644 index 2b7e9555bcd1..000000000000 --- a/arch/h8300/include/asm/switch_to.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_SWITCH_TO_H -#define _H8300_SWITCH_TO_H - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. This - * also clears the TS-flag if the task we switched to has used the - * math co-processor latest. - */ -/* - * switch_to() saves the extra registers, that are not saved - * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and - * a0-a1. Some of these are used by schedule() and its predecessors - * and so we might get see unexpected behaviors when a task returns - * with unexpected register values. - * - * syscall stores these registers itself and none of them are used - * by syscall after the function in the syscall has been called. - * - * Beware that resume now expects *next to be in d1 and the offset of - * tss to be in a1. This saves a few instructions as we no longer have - * to push them onto the stack and read them back right after. - * - * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) - * - * Changed 96/09/19 by Andreas Schwab - * pass prev in a0, next in a1, offset of tss in d1, and whether - * the mm structures are shared in d2 (to avoid atc flushing). - * - * H8/300 Porting 2002/09/04 Yoshinori Sato - */ - -asmlinkage void resume(void); -#define switch_to(prev, next, last) \ -do { \ - void *_last; \ - __asm__ __volatile__( \ - "mov.l %1, er0\n\t" \ - "mov.l %2, er1\n\t" \ - "mov.l %3, er2\n\t" \ - "jsr @_resume\n\t" \ - "mov.l er2,%0\n\t" \ - : "=r" (_last) \ - : "r" (&(prev->thread)), \ - "r" (&(next->thread)), \ - "g" (prev) \ - : "cc", "er0", "er1", "er2", "er3"); \ - (last) = _last; \ -} while (0) - -#endif /* _H8300_SWITCH_TO_H */ diff --git a/arch/h8300/include/asm/syscall.h b/arch/h8300/include/asm/syscall.h deleted file mode 100644 index 01666b8bb263..000000000000 --- a/arch/h8300/include/asm/syscall.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_H8300_SYSCALLS_32_H -#define __ASM_H8300_SYSCALLS_32_H - -#ifdef __KERNEL__ - -#include -#include -#include -#include -#include - -static inline int -syscall_get_nr(struct task_struct *task, struct pt_regs *regs) -{ - return regs->orig_er0; -} - -static inline void -syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, - unsigned long *args) -{ - *args++ = regs->er1; - *args++ = regs->er2; - *args++ = regs->er3; - *args++ = regs->er4; - *args++ = regs->er5; - *args = regs->er6; -} - -static inline int -syscall_get_arch(struct task_struct *task) -{ - return AUDIT_ARCH_H8300; -} - - -/* Misc syscall related bits */ -asmlinkage long do_syscall_trace_enter(struct pt_regs *regs); -asmlinkage void do_syscall_trace_leave(struct pt_regs *regs); - -#endif /* __KERNEL__ */ -#endif /* __ASM_H8300_SYSCALLS_32_H */ diff --git a/arch/h8300/include/asm/thread_info.h b/arch/h8300/include/asm/thread_info.h deleted file mode 100644 index a518214d4ddd..000000000000 --- a/arch/h8300/include/asm/thread_info.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* thread_info.h: h8300 low-level thread information - * adapted from the i386 and PPC versions by Yoshinori Sato - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#include -#include - -#ifdef __KERNEL__ - -/* - * Size of kernel stack for each process. This must be a power of 2... - */ -#define THREAD_SIZE_ORDER 1 -#define THREAD_SIZE 8192 /* 2 pages */ - -#ifndef __ASSEMBLY__ - -/* - * low level task data. - * If you change this, change the TI_* offsets below to match. - */ -struct thread_info { - struct task_struct *task; /* main task structure */ - unsigned long flags; /* low level flags */ - int cpu; /* cpu we're on */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - mm_segment_t addr_limit; -}; - -/* - * macros/functions for gaining access to the thread information structure - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ -} - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - - __asm__("mov.l sp, %0\n\t" - "and.w %1, %T0" - : "=&r"(ti) - : "i" (~(THREAD_SIZE-1) & 0xffff)); - return ti; -} - -#endif /* __ASSEMBLY__ */ - -/* - * thread information flag bit numbers - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_SINGLESTEP 3 /* singlestepping active */ -#define TIF_MEMDIE 4 /* is terminating due to OOM killer */ -#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ -#define TIF_NOTIFY_RESUME 6 /* callback before returning to user */ -#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ -#define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */ -#define TIF_POLLING_NRFLAG 9 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_NOTIFY_SIGNAL 10 /* signal notifications exist */ - -/* as above, but as bit values */ -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) -#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) -#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) -#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) - -/* work to do in syscall trace */ -#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ - _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) - -/* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \ - _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \ - _TIF_SINGLESTEP | _TIF_NOTIFY_RESUME | \ - _TIF_SYSCALL_TRACEPOINT | _TIF_NOTIFY_SIGNAL) - -/* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \ - _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP)) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/h8300/include/asm/tlb.h b/arch/h8300/include/asm/tlb.h deleted file mode 100644 index d8201ca31206..000000000000 --- a/arch/h8300/include/asm/tlb.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __H8300_TLB_H__ -#define __H8300_TLB_H__ - -#include - -#endif diff --git a/arch/h8300/include/asm/traps.h b/arch/h8300/include/asm/traps.h deleted file mode 100644 index 1c5a30ec2df8..000000000000 --- a/arch/h8300/include/asm/traps.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * linux/include/asm-h8300/traps.h - * - * Copyright (C) 2003 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _H8300_TRAPS_H -#define _H8300_TRAPS_H - -extern void _system_call(void); -extern void _interrupt_entry(void); -extern void _trace_break(void); -extern void _nmi(void); -extern void _interrupt_entry(void); - -extern unsigned long *_interrupt_redirect_table; - -#define JMP_OP 0x5a000000 -#define JSR_OP 0x5e000000 -#define VECTOR(address) ((JMP_OP)|((unsigned long)address)) -#define REDIRECT(address) ((JSR_OP)|((unsigned long)address)) -#define CPU_VECTOR ((unsigned long *)0x000000) -#define ADDR_MASK (0xffffff) - -#define TRACE_VEC 5 - -#define TRAP0_VEC 8 -#define TRAP1_VEC 9 -#define TRAP2_VEC 10 -#define TRAP3_VEC 11 - -extern char _start[], _etext[]; -#define check_kernel_text(addr) \ - ((addr >= (unsigned long)(_start)) && \ - (addr < (unsigned long)(_etext)) && !(addr & 1)) - -#endif /* _H8300_TRAPS_H */ diff --git a/arch/h8300/include/asm/user.h b/arch/h8300/include/asm/user.h deleted file mode 100644 index 2298909f24c6..000000000000 --- a/arch/h8300/include/asm/user.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_USER_H -#define _H8300_USER_H - -#include - -/* Core file format: The core file is written in such a way that gdb - can understand it and provide useful information to the user (under - linux we use the 'trad-core' bfd). There are quite a number of - obstacles to being able to view the contents of the floating point - registers, and until these are solved you will not be able to view the - contents of them. Actually, you can read in the core file and look at - the contents of the user struct to find out what the floating point - registers contain. - The actual file contents are as follows: - UPAGE: 1 page consisting of a user struct that tells gdb what is present - in the file. Directly after this is a copy of the task_struct, which - is currently not used by gdb, but it may come in useful at some point. - All of the registers are stored as part of the upage. The upage should - always be only one page. - DATA: The data area is stored. We use current->end_text to - current->brk to pick up all of the user variables, plus any memory - that may have been malloced. No attempt is made to determine if a page - is demand-zero or if a page is totally unused, we just cover the entire - range. All of the addresses are rounded in such a way that an integral - number of pages is written. - STACK: We need the stack information in order to get a meaningful - backtrace. We need to write the data from (esp) to - current->start_stack, so we round each of these off in order to be able - to write an integer number of pages. - The minimum core file size is 3 pages, or 12288 bytes. -*/ - -/* This is the old layout of "struct pt_regs" as of Linux 1.x, and - is still the layout used by user (the new pt_regs doesn't have - all registers). */ -struct user_regs_struct { - long er1, er2, er3, er4, er5, er6; - long er0; - long usp; - long orig_er0; - long ccr; - long pc; -}; - -/* When the kernel dumps core, it starts by dumping the user struct - - this will be used by gdb to figure out where the data and stack segments - are within the file, and what virtual addresses to use. */ -struct user { -/* We start with the registers, to mimic the way that "memory" is returned - from the ptrace(3,...) function. */ - struct user_regs_struct regs; /* Where the registers are actually stored */ -/* ptrace does not yet supply these. Someday.... */ -/* The rest of this junk is to help gdb figure out what goes where */ - unsigned long int u_tsize; /* Text segment size (pages). */ - unsigned long int u_dsize; /* Data segment size (pages). */ - unsigned long int u_ssize; /* Stack segment size (pages). */ - unsigned long start_code; /* Starting virtual address of text. */ - unsigned long start_stack; /* Starting virtual address of stack area. - This is actually the bottom of the stack, - the top of the stack is always found in the - esp register. */ - long int signal; /* Signal that caused the core dump. */ - int reserved; /* No longer used */ - unsigned long u_ar0; /* Used by gdb to help find the values for */ - /* the registers. */ - unsigned long magic; /* To uniquely identify a core file */ - char u_comm[32]; /* User command that was responsible */ -}; -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif diff --git a/arch/h8300/include/asm/vmalloc.h b/arch/h8300/include/asm/vmalloc.h deleted file mode 100644 index 08a55c1dfa23..000000000000 --- a/arch/h8300/include/asm/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_H8300_VMALLOC_H -#define _ASM_H8300_VMALLOC_H - -#endif /* _ASM_H8300_VMALLOC_H */ diff --git a/arch/h8300/include/uapi/asm/Kbuild b/arch/h8300/include/uapi/asm/Kbuild deleted file mode 100644 index e78470141932..000000000000 --- a/arch/h8300/include/uapi/asm/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -generic-y += ucontext.h diff --git a/arch/h8300/include/uapi/asm/byteorder.h b/arch/h8300/include/uapi/asm/byteorder.h deleted file mode 100644 index 1fe2f9344458..000000000000 --- a/arch/h8300/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _H8300_BYTEORDER_H -#define _H8300_BYTEORDER_H - -#include - -#endif /* _H8300_BYTEORDER_H */ diff --git a/arch/h8300/include/uapi/asm/posix_types.h b/arch/h8300/include/uapi/asm/posix_types.h deleted file mode 100644 index 3efc9dd59476..000000000000 --- a/arch/h8300/include/uapi/asm/posix_types.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_POSIX_TYPES_H -#define _UAPI_ASM_POSIX_TYPES_H - -/* h8300-unknown-linux required long */ -#define __kernel_size_t __kernel_size_t -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; - -#include - -#endif /* _UAPI_ASM_POSIX_TYPES_H */ diff --git a/arch/h8300/include/uapi/asm/ptrace.h b/arch/h8300/include/uapi/asm/ptrace.h deleted file mode 100644 index 78167f517ca4..000000000000 --- a/arch/h8300/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_H8300_PTRACE_H -#define _UAPI_H8300_PTRACE_H - -#ifndef __ASSEMBLY__ - -#define PT_ER1 0 -#define PT_ER2 1 -#define PT_ER3 2 -#define PT_ER4 3 -#define PT_ER5 4 -#define PT_ER6 5 -#define PT_ER0 6 -#define PT_USP 7 -#define PT_ORIG_ER0 8 -#define PT_CCR 9 -#define PT_PC 10 -#define PT_EXR 11 - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long retpc; - long er4; - long er5; - long er6; - long er3; - long er2; - long er1; - long orig_er0; - long sp; - unsigned short ccr; - long er0; - long vector; -#if defined(__H8300S__) - unsigned short exr; -#endif - unsigned long pc; -} __attribute__((aligned(2), packed)); - -#endif /* __ASSEMBLY__ */ -#endif /* _UAPI_H8300_PTRACE_H */ diff --git a/arch/h8300/include/uapi/asm/sigcontext.h b/arch/h8300/include/uapi/asm/sigcontext.h deleted file mode 100644 index f77273c857d7..000000000000 --- a/arch/h8300/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_H8300_SIGCONTEXT_H -#define _ASM_H8300_SIGCONTEXT_H - -struct sigcontext { - unsigned long sc_mask; /* old sigmask */ - unsigned long sc_usp; /* old user stack pointer */ - unsigned long sc_er0; - unsigned long sc_er1; - unsigned long sc_er2; - unsigned long sc_er3; - unsigned long sc_er4; - unsigned long sc_er5; - unsigned long sc_er6; - unsigned short sc_ccr; - unsigned long sc_pc; -}; - -#endif diff --git a/arch/h8300/include/uapi/asm/signal.h b/arch/h8300/include/uapi/asm/signal.h deleted file mode 100644 index 2cd0dce2b6a6..000000000000 --- a/arch/h8300/include/uapi/asm/signal.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_H8300_SIGNAL_H -#define _UAPI_H8300_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -#define SA_RESTORER 0x04000000 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - - -#endif /* _UAPI_H8300_SIGNAL_H */ diff --git a/arch/h8300/include/uapi/asm/unistd.h b/arch/h8300/include/uapi/asm/unistd.h deleted file mode 100644 index eb7bc0012af5..000000000000 --- a/arch/h8300/include/uapi/asm/unistd.h +++ /dev/null @@ -1,8 +0,0 @@ -#define __ARCH_NOMMU - -#define __ARCH_WANT_RENAMEAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SET_GET_RLIMIT -#define __ARCH_WANT_TIME32_SYSCALLS - -#include diff --git a/arch/h8300/kernel/.gitignore b/arch/h8300/kernel/.gitignore deleted file mode 100644 index bbb90f92d051..000000000000 --- a/arch/h8300/kernel/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -vmlinux.lds diff --git a/arch/h8300/kernel/Makefile b/arch/h8300/kernel/Makefile deleted file mode 100644 index 307aa51576dd..000000000000 --- a/arch/h8300/kernel/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -extra-y := vmlinux.lds - -obj-y := process.o traps.o ptrace.o \ - signal.o setup.o syscalls.o \ - irq.o entry.o - -obj-$(CONFIG_ROMKERNEL) += head_rom.o -obj-$(CONFIG_RAMKERNEL) += head_ram.o - -obj-$(CONFIG_MODULES) += module.o h8300_ksyms.o -obj-$(CONFIG_H8300H_SIM) += sim-console.o -obj-$(CONFIG_H8S_SIM) += sim-console.o - -obj-$(CONFIG_CPU_H8300H) += ptrace_h.o -obj-$(CONFIG_CPU_H8S) += ptrace_s.o - -obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/h8300/kernel/asm-offsets.c b/arch/h8300/kernel/asm-offsets.c deleted file mode 100644 index 65571ee15132..000000000000 --- a/arch/h8300/kernel/asm-offsets.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -int main(void) -{ - /* offsets into the task struct */ - OFFSET(TASK_FLAGS, task_struct, flags); - OFFSET(TASK_PTRACE, task_struct, ptrace); - OFFSET(TASK_BLOCKED, task_struct, blocked); - OFFSET(TASK_THREAD, task_struct, thread); - OFFSET(TASK_THREAD_INFO, task_struct, stack); - OFFSET(TASK_MM, task_struct, mm); - OFFSET(TASK_ACTIVE_MM, task_struct, active_mm); - - /* offsets into the irq_cpustat_t struct */ - DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, - __softirq_pending)); - - /* offsets into the thread struct */ - OFFSET(THREAD_KSP, thread_struct, ksp); - OFFSET(THREAD_USP, thread_struct, usp); - OFFSET(THREAD_CCR, thread_struct, ccr); - - /* offsets into the pt_regs struct */ - DEFINE(LER0, offsetof(struct pt_regs, er0) - sizeof(long)); - DEFINE(LER1, offsetof(struct pt_regs, er1) - sizeof(long)); - DEFINE(LER2, offsetof(struct pt_regs, er2) - sizeof(long)); - DEFINE(LER3, offsetof(struct pt_regs, er3) - sizeof(long)); - DEFINE(LER4, offsetof(struct pt_regs, er4) - sizeof(long)); - DEFINE(LER5, offsetof(struct pt_regs, er5) - sizeof(long)); - DEFINE(LER6, offsetof(struct pt_regs, er6) - sizeof(long)); - DEFINE(LORIG, offsetof(struct pt_regs, orig_er0) - sizeof(long)); - DEFINE(LSP, offsetof(struct pt_regs, sp) - sizeof(long)); - DEFINE(LCCR, offsetof(struct pt_regs, ccr) - sizeof(long)); - DEFINE(LVEC, offsetof(struct pt_regs, vector) - sizeof(long)); -#if defined(CONFIG_CPU_H8S) - DEFINE(LEXR, offsetof(struct pt_regs, exr) - sizeof(long)); -#endif - DEFINE(LRET, offsetof(struct pt_regs, pc) - sizeof(long)); - - DEFINE(PT_PTRACED, PT_PTRACED); - - /* offsets in thread_info structure */ - OFFSET(TI_TASK, thread_info, task); - OFFSET(TI_FLAGS, thread_info, flags); - OFFSET(TI_CPU, thread_info, cpu); - OFFSET(TI_PRE, thread_info, preempt_count); -#ifdef CONFIG_PREEMPTION - DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count)); -#endif - - return 0; -} diff --git a/arch/h8300/kernel/entry.S b/arch/h8300/kernel/entry.S deleted file mode 100644 index c6e289b5f1f2..000000000000 --- a/arch/h8300/kernel/entry.S +++ /dev/null @@ -1,434 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * - * linux/arch/h8300/kernel/entry.S - * - * Yoshinori Sato - * David McCullough - * - */ - -/* - * entry.S - * include exception/interrupt gateway - * system call entry - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CPU_H8300H) -#define USERRET 8 -INTERRUPTS = 64 - .h8300h - .macro SHLL2 reg - shll.l \reg - shll.l \reg - .endm - .macro SHLR2 reg - shlr.l \reg - shlr.l \reg - .endm - .macro SAVEREGS - mov.l er0,@-sp - mov.l er1,@-sp - mov.l er2,@-sp - mov.l er3,@-sp - .endm - .macro RESTOREREGS - mov.l @sp+,er3 - mov.l @sp+,er2 - .endm - .macro SAVEEXR - .endm - .macro RESTOREEXR - .endm -#endif -#if defined(CONFIG_CPU_H8S) -#define USERRET 10 -#define USEREXR 8 -INTERRUPTS = 128 - .h8300s - .macro SHLL2 reg - shll.l #2,\reg - .endm - .macro SHLR2 reg - shlr.l #2,\reg - .endm - .macro SAVEREGS - stm.l er0-er3,@-sp - .endm - .macro RESTOREREGS - ldm.l @sp+,er2-er3 - .endm - .macro SAVEEXR - mov.w @(USEREXR:16,er0),r1 - mov.w r1,@(LEXR-LER3:16,sp) /* copy EXR */ - .endm - .macro RESTOREEXR - mov.w @(LEXR-LER1:16,sp),r1 /* restore EXR */ - mov.b r1l,r1h - mov.w r1,@(USEREXR:16,er0) - .endm -#endif - - -/* CPU context save/restore macros. */ - - .macro SAVE_ALL - mov.l er0,@-sp - stc ccr,r0l /* check kernel mode */ - btst #4,r0l - bne 5f - - /* user mode */ - mov.l sp,@_sw_usp - mov.l @sp,er0 /* restore saved er0 */ - orc #0x10,ccr /* switch kernel stack */ - mov.l @_sw_ksp,sp - sub.l #(LRET-LORIG),sp /* allocate LORIG - LRET */ - SAVEREGS - mov.l @_sw_usp,er0 - mov.l @(USERRET:16,er0),er1 /* copy the RET addr */ - mov.l er1,@(LRET-LER3:16,sp) - SAVEEXR - - mov.l @(LORIG-LER3:16,sp),er0 - mov.l er0,@(LER0-LER3:16,sp) /* copy ER0 */ - mov.w e1,r1 /* e1 highbyte = ccr */ - and #0xef,r1h /* mask mode? flag */ - bra 6f -5: - /* kernel mode */ - mov.l @sp,er0 /* restore saved er0 */ - subs #2,sp /* set dummy ccr */ - subs #4,sp /* set dummp sp */ - SAVEREGS - mov.w @(LRET-LER3:16,sp),r1 /* copy old ccr */ -6: - mov.b r1h,r1l - mov.b #0,r1h - mov.w r1,@(LCCR-LER3:16,sp) /* set ccr */ - mov.l @_sw_usp,er2 - mov.l er2,@(LSP-LER3:16,sp) /* set usp */ - mov.l er6,@-sp /* syscall arg #6 */ - mov.l er5,@-sp /* syscall arg #5 */ - mov.l er4,@-sp /* syscall arg #4 */ - .endm /* r1 = ccr */ - - .macro RESTORE_ALL - mov.l @sp+,er4 - mov.l @sp+,er5 - mov.l @sp+,er6 - RESTOREREGS - mov.w @(LCCR-LER1:16,sp),r0 /* check kernel mode */ - btst #4,r0l - bne 7f - - orc #0xc0,ccr - mov.l @(LSP-LER1:16,sp),er0 - mov.l @(LER0-LER1:16,sp),er1 /* restore ER0 */ - mov.l er1,@er0 - RESTOREEXR - mov.w @(LCCR-LER1:16,sp),r1 /* restore the RET addr */ - mov.b r1l,r1h - mov.b @(LRET+1-LER1:16,sp),r1l - mov.w r1,e1 - mov.w @(LRET+2-LER1:16,sp),r1 - mov.l er1,@(USERRET:16,er0) - - mov.l @sp+,er1 - add.l #(LRET-LER1),sp /* remove LORIG - LRET */ - mov.l sp,@_sw_ksp - andc #0xef,ccr /* switch to user mode */ - mov.l er0,sp - bra 8f -7: - mov.l @sp+,er1 - add.l #10,sp -8: - mov.l @sp+,er0 - adds #4,sp /* remove the sw created LVEC */ - rte - .endm - -.globl _system_call -.globl ret_from_exception -.globl ret_from_fork -.globl ret_from_kernel_thread -.globl ret_from_interrupt -.globl _interrupt_redirect_table -.globl _sw_ksp,_sw_usp -.globl _resume -.globl _interrupt_entry -.globl _trace_break -.globl _nmi - -#if defined(CONFIG_ROMKERNEL) - .section .int_redirect,"ax" -_interrupt_redirect_table: -#if defined(CONFIG_CPU_H8300H) - .rept 7 - .long 0 - .endr -#endif -#if defined(CONFIG_CPU_H8S) - .rept 5 - .long 0 - .endr - jmp @_trace_break - .long 0 -#endif - - jsr @_interrupt_entry /* NMI */ - jmp @_system_call /* TRAPA #0 (System call) */ - .long 0 -#if defined(CONFIG_KGDB) - jmp @_kgdb_trap -#else - .long 0 -#endif - jmp @_trace_break /* TRAPA #3 (breakpoint) */ - .rept INTERRUPTS-12 - jsr @_interrupt_entry - .endr -#endif -#if defined(CONFIG_RAMKERNEL) -.globl _interrupt_redirect_table - .section .bss -_interrupt_redirect_table: - .space 4 -#endif - - .section .text - .align 2 -_interrupt_entry: - SAVE_ALL -/* r1l is saved ccr */ - mov.l sp,er0 - add.l #LVEC,er0 - btst #4,r1l - bne 1f - /* user LVEC */ - mov.l @_sw_usp,er0 - adds #4,er0 -1: - mov.l @er0,er0 /* LVEC address */ -#if defined(CONFIG_ROMKERNEL) - sub.l #_interrupt_redirect_table,er0 -#endif -#if defined(CONFIG_RAMKERNEL) - mov.l @_interrupt_redirect_table,er1 - sub.l er1,er0 -#endif - SHLR2 er0 - dec.l #1,er0 - mov.l sp,er1 - subs #4,er1 /* adjust ret_pc */ -#if defined(CONFIG_CPU_H8S) - orc #7,exr -#endif - jsr @do_IRQ - jmp @ret_from_interrupt - -_system_call: - subs #4,sp /* dummy LVEC */ - SAVE_ALL - /* er0: syscall nr */ - andc #0xbf,ccr - mov.l er0,er4 - - /* save top of frame */ - mov.l sp,er0 - jsr @set_esp0 - andc #0x3f,ccr - mov.l sp,er2 - and.w #0xe000,r2 - mov.l @(TI_FLAGS:16,er2),er2 - and.w #_TIF_WORK_SYSCALL_MASK,r2 - beq 1f - mov.l sp,er0 - jsr @do_syscall_trace_enter -1: - cmp.l #__NR_syscalls,er4 - bcc badsys - SHLL2 er4 - mov.l #_sys_call_table,er0 - add.l er4,er0 - mov.l @er0,er4 - beq ret_from_exception:16 - mov.l @(LER1:16,sp),er0 - mov.l @(LER2:16,sp),er1 - mov.l @(LER3:16,sp),er2 - jsr @er4 - mov.l er0,@(LER0:16,sp) /* save the return value */ - mov.l sp,er2 - and.w #0xe000,r2 - mov.l @(TI_FLAGS:16,er2),er2 - and.w #_TIF_WORK_SYSCALL_MASK,r2 - beq 2f - mov.l sp,er0 - jsr @do_syscall_trace_leave -2: - orc #0xc0,ccr - bra resume_userspace - -badsys: - mov.l #-ENOSYS,er0 - mov.l er0,@(LER0:16,sp) - bra resume_userspace - -#if !defined(CONFIG_PREEMPTION) -#define resume_kernel restore_all -#endif - -ret_from_exception: -#if defined(CONFIG_PREEMPTION) - orc #0xc0,ccr -#endif -ret_from_interrupt: - mov.b @(LCCR+1:16,sp),r0l - btst #4,r0l - bne resume_kernel:16 /* return from kernel */ -resume_userspace: - andc #0xbf,ccr - mov.l sp,er4 - and.w #0xe000,r4 /* er4 <- current thread info */ - mov.l @(TI_FLAGS:16,er4),er1 - and.l #_TIF_WORK_MASK,er1 - beq restore_all:8 -work_pending: - btst #TIF_NEED_RESCHED,r1l - bne work_resched:8 - /* work notifysig */ - mov.l sp,er0 - subs #4,er0 /* er0: pt_regs */ - jsr @do_notify_resume - bra resume_userspace:8 -work_resched: - mov.l sp,er0 - jsr @set_esp0 - jsr @schedule - bra resume_userspace:8 -restore_all: - RESTORE_ALL /* Does RTE */ - -#if defined(CONFIG_PREEMPTION) -resume_kernel: - mov.l @(TI_PRE_COUNT:16,er4),er0 - bne restore_all:8 -need_resched: - mov.l @(TI_FLAGS:16,er4),er0 - btst #TIF_NEED_RESCHED,r0l - beq restore_all:8 - mov.b @(LCCR+1:16,sp),r0l /* Interrupt Enabled? */ - bmi restore_all:8 - mov.l sp,er0 - jsr @set_esp0 - jsr @preempt_schedule_irq - bra need_resched:8 -#endif - -ret_from_fork: - mov.l er2,er0 - jsr @schedule_tail - jmp @ret_from_exception - -ret_from_kernel_thread: - mov.l er2,er0 - jsr @schedule_tail - mov.l @(LER4:16,sp),er0 - mov.l @(LER5:16,sp),er1 - jsr @er1 - jmp @ret_from_exception - -_resume: - /* - * Beware - when entering resume, offset of tss is in d1, - * prev (the current task) is in a0, next (the new task) - * is in a1 and d2.b is non-zero if the mm structure is - * shared between the tasks, so don't change these - * registers until their contents are no longer needed. - */ - - /* save sr */ - sub.w r3,r3 - stc ccr,r3l - mov.w r3,@(THREAD_CCR+2:16,er0) - - /* disable interrupts */ - orc #0xc0,ccr - mov.l @_sw_usp,er3 - mov.l er3,@(THREAD_USP:16,er0) - mov.l sp,@(THREAD_KSP:16,er0) - - /* Skip address space switching if they are the same. */ - /* FIXME: what did we hack out of here, this does nothing! */ - - mov.l @(THREAD_USP:16,er1),er0 - mov.l er0,@_sw_usp - mov.l @(THREAD_KSP:16,er1),sp - - /* restore status register */ - mov.w @(THREAD_CCR+2:16,er1),r3 - - ldc r3l,ccr - rts - -_trace_break: - subs #4,sp - SAVE_ALL - sub.l er1,er1 - dec.l #1,er1 - mov.l er1,@(LORIG,sp) - mov.l sp,er0 - jsr @set_esp0 - mov.l @_sw_usp,er0 - mov.l @er0,er1 - mov.w @(-2:16,er1),r2 - cmp.w #0x5730,r2 - beq 1f - subs #2,er1 - mov.l er1,@er0 -1: - and.w #0xff,e1 - mov.l er1,er0 - jsr @trace_trap - jmp @ret_from_exception - -_nmi: - subs #4, sp - mov.l er0, @-sp - mov.l @_interrupt_redirect_table, er0 - add.l #8*4, er0 - mov.l er0, @(4,sp) - mov.l @sp+, er0 - jmp @_interrupt_entry - -#if defined(CONFIG_KGDB) -_kgdb_trap: - subs #4,sp - SAVE_ALL - mov.l sp,er0 - add.l #LRET,er0 - mov.l er0,@(LSP,sp) - jsr @set_esp0 - mov.l sp,er0 - subs #4,er0 - jsr @h8300_kgdb_trap - jmp @ret_from_exception -#endif - - .section .bss -_sw_ksp: - .space 4 -_sw_usp: - .space 4 - - .end diff --git a/arch/h8300/kernel/h8300_ksyms.c b/arch/h8300/kernel/h8300_ksyms.c deleted file mode 100644 index 853d6e886477..000000000000 --- a/arch/h8300/kernel/h8300_ksyms.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -/* - * libgcc functions - functions that are used internally by the - * compiler... (prototypes are not correct though, but that - * doesn't really matter since they're not versioned). - */ -asmlinkage long __ucmpdi2(long long, long long); -asmlinkage long long __ashldi3(long long, int); -asmlinkage long long __ashrdi3(long long, int); -asmlinkage long long __lshrdi3(long long, int); -asmlinkage long __divsi3(long, long); -asmlinkage long __modsi3(long, long); -asmlinkage unsigned long __umodsi3(unsigned long, unsigned long); -asmlinkage long long __muldi3(long long, long long); -asmlinkage long __mulsi3(long, long); -asmlinkage long __udivsi3(long, long); -asmlinkage void *memcpy(void *, const void *, size_t); -asmlinkage void *memset(void *, int, size_t); - - /* gcc lib functions */ -EXPORT_SYMBOL(__ucmpdi2); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__divsi3); -EXPORT_SYMBOL(__modsi3); -EXPORT_SYMBOL(__umodsi3); -EXPORT_SYMBOL(__muldi3); -EXPORT_SYMBOL(__mulsi3); -EXPORT_SYMBOL(__udivsi3); -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memset); diff --git a/arch/h8300/kernel/head_ram.S b/arch/h8300/kernel/head_ram.S deleted file mode 100644 index dbf8429f5fab..000000000000 --- a/arch/h8300/kernel/head_ram.S +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CPU_H8300H) - .h8300h -#define SYSCR 0xfee012 -#define IRAMTOP 0xffff20 -#endif -#if defined(CONFIG_CPU_H8S) - .h8300s -#define INTCR 0xffff31 -#define IRAMTOP 0xffc000 -#endif - - __HEAD - .global _start -_start: - mov.l #IRAMTOP,sp - /* .bss clear */ - mov.l #_sbss,er5 - mov.l #_ebss,er4 - sub.l er5,er4 - shlr er4 - shlr er4 - sub.l er2,er2 -1: - mov.l er2,@er5 - adds #4,er5 - dec.l #1,er4 - bne 1b - jsr @h8300_fdt_init - - /* linux kernel start */ -#if defined(CONFIG_CPU_H8300H) - ldc #0xd0,ccr /* running kernel */ - mov.l #SYSCR,er0 - bclr #3,@er0 -#endif -#if defined(CONFIG_CPU_H8S) - ldc #0x07,exr - bclr #4,@INTCR:8 - bset #5,@INTCR:8 /* Interrupt mode 2 */ - ldc #0x90,ccr /* running kernel */ -#endif - mov.l #init_thread_union,sp - add.l #0x2000,sp - jsr @start_kernel - -1: - bra 1b - - .end diff --git a/arch/h8300/kernel/head_rom.S b/arch/h8300/kernel/head_rom.S deleted file mode 100644 index ab55a9cb2f36..000000000000 --- a/arch/h8300/kernel/head_rom.S +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include -#include - -#if defined(CONFIG_CPU_H8300H) - .h8300h -#define SYSCR 0xfee012 -#define IRAMTOP 0xffff20 -#define NR_INT 64 -#endif -#if defined(CONFIG_CPU_H8S) - .h8300s -#define INTCR 0xffff31 -#define IRAMTOP 0xffc000 -#define NR_INT 128 -#endif - - __HEAD - .global _start -_start: - mov.l #IRAMTOP,sp -#if !defined(CONFIG_H8300H_SIM) && \ - !defined(CONFIG_H8S_SIM) - jsr @lowlevel_init - - /* copy .data */ - mov.l #_begin_data,er5 - mov.l #_sdata,er6 - mov.l #_edata,er4 - sub.l er6,er4 - shlr.l er4 - shlr.l er4 -1: - mov.l @er5+,er0 - mov.l er0,@er6 - adds #4,er6 - dec.l #1,er4 - bne 1b - /* .bss clear */ - mov.l #_sbss,er5 - mov.l #_ebss,er4 - sub.l er5,er4 - shlr er4 - shlr er4 - sub.l er0,er0 -1: - mov.l er0,@er5 - adds #4,er5 - dec.l #1,er4 - bne 1b -#else - /* get cmdline from gdb */ - jsr @0xcc - ;; er0 - argc - ;; er1 - argv - mov.l #command_line,er3 - adds #4,er1 - dec.l #1,er0 - beq 4f -1: - mov.l @er1+,er2 -2: - mov.b @er2+,r4l - beq 3f - mov.b r4l,@er3 - adds #1,er3 - bra 2b -3: - mov.b #' ',r4l - mov.b r4l,@er3 - adds #1,er3 - dec.l #1,er0 - bne 1b - subs #1,er3 - mov.b #0,r4l - mov.b r4l,@er3 -4: -#endif - sub.l er0,er0 - jsr @h8300_fdt_init - /* linux kernel start */ -#if defined(CONFIG_CPU_H8300H) - ldc #0xd0,ccr /* running kernel */ - mov.l #SYSCR,er0 - bclr #3,@er0 -#endif -#if defined(CONFIG_CPU_H8S) - ldc #0x07,exr - bclr #4,@INTCR:8 - bset #5,@INTCR:8 /* Interrupt mode 2 */ - ldc #0x90,ccr /* running kernel */ -#endif - mov.l #init_thread_union,sp - add.l #0x2000,sp - jsr @start_kernel - -1: - bra 1b - -#if defined(CONFIG_ROMKERNEL) - /* interrupt vector */ - .section .vectors,"ax" - .long _start - .long _start -vector = 2 - .rept NR_INT - 2 - .long _interrupt_redirect_table+vector*4 -vector = vector + 1 - .endr -#endif - .end diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c deleted file mode 100644 index 8ad6d702cd0b..000000000000 --- a/arch/h8300/kernel/irq.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/kernel/irq.c - * - * Copyright 2014-2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_RAMKERNEL -typedef void (*h8300_vector)(void); - -static const h8300_vector __initconst trap_table[] = { - 0, 0, 0, 0, - _trace_break, - 0, 0, - _nmi, - _system_call, - 0, 0, - _trace_break, -}; - -static unsigned long __init *get_vector_address(void) -{ - unsigned long *rom_vector = CPU_VECTOR; - unsigned long base, tmp; - int vec_no; - - base = rom_vector[EXT_IRQ0] & ADDR_MASK; - - /* check romvector format */ - for (vec_no = EXT_IRQ0 + 1; vec_no <= EXT_IRQ0+EXT_IRQS; vec_no++) { - if ((base+(vec_no - EXT_IRQ0)*4) != - (rom_vector[vec_no] & ADDR_MASK)) - return NULL; - } - - /* ramvector base address */ - base -= EXT_IRQ0*4; - - /* writerble? */ - tmp = ~(*(volatile unsigned long *)base); - (*(volatile unsigned long *)base) = tmp; - if ((*(volatile unsigned long *)base) != tmp) - return NULL; - return (unsigned long *)base; -} - -static void __init setup_vector(void) -{ - int i; - unsigned long *ramvec, *ramvec_p; - const h8300_vector *trap_entry; - - ramvec = get_vector_address(); - if (ramvec == NULL) - panic("interrupt vector serup failed."); - else - pr_debug("virtual vector at 0x%p\n", ramvec); - - /* create redirect table */ - ramvec_p = ramvec; - trap_entry = trap_table; - for (i = 0; i < NR_IRQS; i++) { - if (i < 12) { - if (*trap_entry) - *ramvec_p = VECTOR(*trap_entry); - ramvec_p++; - trap_entry++; - } else - *ramvec_p++ = REDIRECT(_interrupt_entry); - } - _interrupt_redirect_table = ramvec; -} -#else -void setup_vector(void) -{ - /* noting do */ -} -#endif - -void __init init_IRQ(void) -{ - setup_vector(); - irqchip_init(); -} - -asmlinkage void do_IRQ(int irq) -{ - irq_enter(); - generic_handle_irq(irq); - irq_exit(); -} diff --git a/arch/h8300/kernel/kgdb.c b/arch/h8300/kernel/kgdb.c deleted file mode 100644 index 602e478afbd5..000000000000 --- a/arch/h8300/kernel/kgdb.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * H8/300 KGDB support - * - * Copyright (C) 2015 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include - -struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { - { "er0", GDB_SIZEOF_REG, offsetof(struct pt_regs, er0) }, - { "er1", GDB_SIZEOF_REG, offsetof(struct pt_regs, er1) }, - { "er2", GDB_SIZEOF_REG, offsetof(struct pt_regs, er2) }, - { "er3", GDB_SIZEOF_REG, offsetof(struct pt_regs, er3) }, - { "er4", GDB_SIZEOF_REG, offsetof(struct pt_regs, er4) }, - { "er5", GDB_SIZEOF_REG, offsetof(struct pt_regs, er5) }, - { "er6", GDB_SIZEOF_REG, offsetof(struct pt_regs, er6) }, - { "sp", GDB_SIZEOF_REG, offsetof(struct pt_regs, sp) }, - { "ccr", GDB_SIZEOF_REG, offsetof(struct pt_regs, ccr) }, - { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, pc) }, - { "cycles", GDB_SIZEOF_REG, -1 }, -#if defined(CONFIG_CPU_H8S) - { "exr", GDB_SIZEOF_REG, offsetof(struct pt_regs, exr) }, -#endif - { "tick", GDB_SIZEOF_REG, -1 }, - { "inst", GDB_SIZEOF_REG, -1 }, -}; - -char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) -{ - if (regno >= DBG_MAX_REG_NUM || regno < 0) - return NULL; - - switch (regno) { - case GDB_CCR: -#if defined(CONFIG_CPU_H8S) - case GDB_EXR: -#endif - *(u32 *)mem = *(u16 *)((void *)regs + - dbg_reg_def[regno].offset); - break; - default: - if (dbg_reg_def[regno].offset >= 0) - memcpy(mem, (void *)regs + dbg_reg_def[regno].offset, - dbg_reg_def[regno].size); - else - memset(mem, 0, dbg_reg_def[regno].size); - break; - } - return dbg_reg_def[regno].name; -} - -int dbg_set_reg(int regno, void *mem, struct pt_regs *regs) -{ - if (regno >= DBG_MAX_REG_NUM || regno < 0) - return -EINVAL; - - switch (regno) { - case GDB_CCR: -#if defined(CONFIG_CPU_H8S) - case GDB_EXR: -#endif - *(u16 *)((void *)regs + - dbg_reg_def[regno].offset) = *(u32 *)mem; - break; - default: - memcpy((void *)regs + dbg_reg_def[regno].offset, mem, - dbg_reg_def[regno].size); - } - return 0; -} - -asmlinkage void h8300_kgdb_trap(struct pt_regs *regs) -{ - regs->pc &= 0x00ffffff; - if (kgdb_handle_exception(10, SIGTRAP, 0, regs)) - return; - if (*(u16 *)(regs->pc) == *(u16 *)&arch_kgdb_ops.gdb_bpt_instr) - regs->pc += BREAK_INSTR_SIZE; - regs->pc |= regs->ccr << 24; -} - -void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) -{ - memset((char *)gdb_regs, 0, NUMREGBYTES); - gdb_regs[GDB_SP] = p->thread.ksp; - gdb_regs[GDB_PC] = KSTK_EIP(p); -} - -void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) -{ - regs->pc = pc; -} - -int kgdb_arch_handle_exception(int vector, int signo, int err_code, - char *remcom_in_buffer, char *remcom_out_buffer, - struct pt_regs *regs) -{ - char *ptr; - unsigned long addr; - - switch (remcom_in_buffer[0]) { - case 's': - case 'c': - /* handle the optional parameters */ - ptr = &remcom_in_buffer[1]; - if (kgdb_hex2long(&ptr, &addr)) - regs->pc = addr; - - return 0; - } - - return -1; /* this means that we do not want to exit from the handler */ -} - -int kgdb_arch_init(void) -{ - return 0; -} - -void kgdb_arch_exit(void) -{ - /* Nothing to do */ -} - -const struct kgdb_arch arch_kgdb_ops = { - /* Breakpoint instruction: trapa #2 */ - .gdb_bpt_instr = { 0x57, 0x20 }, -}; diff --git a/arch/h8300/kernel/module.c b/arch/h8300/kernel/module.c deleted file mode 100644 index cd802cc78d97..000000000000 --- a/arch/h8300/kernel/module.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr; - - pr_debug("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rela); i++) { - /* This is where to make the change */ - uint32_t *loc = - (uint32_t *)(sechdrs[sechdrs[relsec].sh_info].sh_addr - + rela[i].r_offset); - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - Elf32_Sym *sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rela[i].r_info); - uint32_t v = sym->st_value + rela[i].r_addend; - - switch (ELF32_R_TYPE(rela[i].r_info)) { - case R_H8_DIR24R8: - loc = (uint32_t *)((uint32_t)loc - 1); - *loc = (*loc & 0xff000000) | ((*loc & 0xffffff) + v); - break; - case R_H8_DIR24A8: - if (ELF32_R_SYM(rela[i].r_info)) - *loc += v; - break; - case R_H8_DIR32: - case R_H8_DIR32A16: - *loc += v; - break; - case R_H8_PCREL16: - v -= (unsigned long)loc + 2; - if ((Elf32_Sword)v > 0x7fff || - (Elf32_Sword)v < -(Elf32_Sword)0x8000) - goto overflow; - else - *(unsigned short *)loc = v; - break; - case R_H8_PCREL8: - v -= (unsigned long)loc + 1; - if ((Elf32_Sword)v > 0x7f || - (Elf32_Sword)v < -(Elf32_Sword)0x80) - goto overflow; - else - *(unsigned char *)loc = v; - break; - default: - pr_err("module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rela[i].r_info)); - return -ENOEXEC; - } - } - return 0; - overflow: - pr_err("module %s: relocation offset overflow: %08x\n", - me->name, rela[i].r_offset); - return -ENOEXEC; -} diff --git a/arch/h8300/kernel/process.c b/arch/h8300/kernel/process.c deleted file mode 100644 index 8833fa4f5d51..000000000000 --- a/arch/h8300/kernel/process.c +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/kernel/process.c - * - * Yoshinori Sato - * - * Based on: - * - * linux/arch/m68knommu/kernel/process.c - * - * Copyright (C) 1998 D. Jeff Dionne , - * Kenneth Albanowski , - * The Silver Hammer Group, Ltd. - * - * linux/arch/m68k/kernel/process.c - * - * Copyright (C) 1995 Hamish Macdonald - * - * 68060 fixes by Jesper Skov - */ - -/* - * This file handles the architecture-dependent parts of process handling.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -void (*pm_power_off)(void) = NULL; -EXPORT_SYMBOL(pm_power_off); - -asmlinkage void ret_from_fork(void); -asmlinkage void ret_from_kernel_thread(void); - -/* - * The idle loop on an H8/300.. - */ -void arch_cpu_idle(void) -{ - raw_local_irq_enable(); - __asm__("sleep"); -} - -void machine_restart(char *__unused) -{ - local_irq_disable(); - __asm__("jmp @@0"); -} - -void machine_halt(void) -{ - local_irq_disable(); - __asm__("sleep"); - for (;;) - ; -} - -void machine_power_off(void) -{ - local_irq_disable(); - __asm__("sleep"); - for (;;) - ; -} - -void show_regs(struct pt_regs *regs) -{ - show_regs_print_info(KERN_DEFAULT); - - pr_notice("\n"); - pr_notice("PC: %08lx Status: %02x\n", - regs->pc, regs->ccr); - pr_notice("ORIG_ER0: %08lx ER0: %08lx ER1: %08lx\n", - regs->orig_er0, regs->er0, regs->er1); - pr_notice("ER2: %08lx ER3: %08lx ER4: %08lx ER5: %08lx\n", - regs->er2, regs->er3, regs->er4, regs->er5); - pr_notice("ER6' %08lx ", regs->er6); - if (user_mode(regs)) - printk("USP: %08lx\n", rdusp()); - else - printk("\n"); -} - -void flush_thread(void) -{ -} - -int copy_thread(unsigned long clone_flags, unsigned long usp, - unsigned long topstk, struct task_struct *p, unsigned long tls) -{ - struct pt_regs *childregs; - - childregs = (struct pt_regs *) (THREAD_SIZE + task_stack_page(p)) - 1; - - if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) { - memset(childregs, 0, sizeof(struct pt_regs)); - childregs->retpc = (unsigned long) ret_from_kernel_thread; - childregs->er4 = topstk; /* arg */ - childregs->er5 = usp; /* fn */ - } else { - *childregs = *current_pt_regs(); - childregs->er0 = 0; - childregs->retpc = (unsigned long) ret_from_fork; - p->thread.usp = usp ?: rdusp(); - } - p->thread.ksp = (unsigned long)childregs; - - return 0; -} - -unsigned long __get_wchan(struct task_struct *p) -{ - unsigned long fp, pc; - unsigned long stack_page; - int count = 0; - - stack_page = (unsigned long)p; - fp = ((struct pt_regs *)p->thread.ksp)->er6; - do { - if (fp < stack_page+sizeof(struct thread_info) || - fp >= 8184+stack_page) - return 0; - pc = ((unsigned long *)fp)[1]; - if (!in_sched_functions(pc)) - return pc; - fp = *(unsigned long *) fp; - } while (count++ < 16); - return 0; -} - -/* generic sys_clone is not enough registers */ -asmlinkage int sys_clone(unsigned long __user *args) -{ - unsigned long clone_flags; - unsigned long newsp; - uintptr_t parent_tidptr; - uintptr_t child_tidptr; - struct kernel_clone_args kargs = {}; - - get_user(clone_flags, &args[0]); - get_user(newsp, &args[1]); - get_user(parent_tidptr, &args[2]); - get_user(child_tidptr, &args[3]); - - kargs.flags = (lower_32_bits(clone_flags) & ~CSIGNAL); - kargs.pidfd = (int __user *)parent_tidptr; - kargs.child_tid = (int __user *)child_tidptr; - kargs.parent_tid = (int __user *)parent_tidptr; - kargs.exit_signal = (lower_32_bits(clone_flags) & CSIGNAL); - kargs.stack = newsp; - - return kernel_clone(&kargs); -} diff --git a/arch/h8300/kernel/ptrace.c b/arch/h8300/kernel/ptrace.c deleted file mode 100644 index a11db009d0ea..000000000000 --- a/arch/h8300/kernel/ptrace.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * linux/arch/h8300/kernel/ptrace.c - * - * Copyright 2015 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of - * this archive for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define CCR_MASK 0x6f /* mode/imask not set */ -#define EXR_MASK 0x80 /* modify only T */ - -#define PT_REG(r) offsetof(struct pt_regs, r) - -extern void user_disable_single_step(struct task_struct *child); - -/* Mapping from PT_xxx to the stack offset at which the register is - saved. Notice that usp has no stack-slot and needs to be treated - specially (see get_reg/put_reg below). */ -static const int register_offset[] = { - PT_REG(er1), PT_REG(er2), PT_REG(er3), PT_REG(er4), - PT_REG(er5), PT_REG(er6), PT_REG(er0), -1, - PT_REG(orig_er0), PT_REG(ccr), PT_REG(pc), -#if defined(CONFIG_CPU_H8S) - PT_REG(exr), -#endif -}; - -/* read register */ -long h8300_get_reg(struct task_struct *task, int regno) -{ - switch (regno) { - case PT_USP: - return task->thread.usp + sizeof(long)*2; - case PT_CCR: - case PT_EXR: - return *(unsigned short *)(task->thread.esp0 + - register_offset[regno]); - default: - return *(unsigned long *)(task->thread.esp0 + - register_offset[regno]); - } -} - -int h8300_put_reg(struct task_struct *task, int regno, unsigned long data) -{ - unsigned short oldccr; - unsigned short oldexr; - - switch (regno) { - case PT_USP: - task->thread.usp = data - sizeof(long)*2; - case PT_CCR: - oldccr = *(unsigned short *)(task->thread.esp0 + - register_offset[regno]); - oldccr &= ~CCR_MASK; - data &= CCR_MASK; - data |= oldccr; - *(unsigned short *)(task->thread.esp0 + - register_offset[regno]) = data; - break; - case PT_EXR: - oldexr = *(unsigned short *)(task->thread.esp0 + - register_offset[regno]); - oldccr &= ~EXR_MASK; - data &= EXR_MASK; - data |= oldexr; - *(unsigned short *)(task->thread.esp0 + - register_offset[regno]) = data; - break; - default: - *(unsigned long *)(task->thread.esp0 + - register_offset[regno]) = data; - break; - } - return 0; -} - -static int regs_get(struct task_struct *target, - const struct user_regset *regset, - struct membuf to) -{ - int r; - - BUILD_BUG_ON(sizeof(struct user_regs_struct) % sizeof(long) != 0); - for (r = 0; r < ELF_NGREG; r++) - membuf_store(&to, h8300_get_reg(target, r)); - - return 0; -} - -static int regs_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - int r; - int ret; - struct user_regs_struct regs; - long *reg; - - /* build user regs in buffer */ - BUILD_BUG_ON(sizeof(regs) % sizeof(long) != 0); - for (reg = (long *)®s, r = 0; r < sizeof(regs) / sizeof(long); r++) - *reg++ = h8300_get_reg(target, r); - - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - ®s, 0, sizeof(regs)); - if (ret) - return ret; - - /* write back to pt_regs */ - for (reg = (long *)®s, r = 0; r < sizeof(regs) / sizeof(long); r++) - h8300_put_reg(target, r, *reg++); - return 0; -} - -enum h8300_regset { - REGSET_GENERAL, -}; - -static const struct user_regset h8300_regsets[] = { - [REGSET_GENERAL] = { - .core_note_type = NT_PRSTATUS, - .n = ELF_NGREG, - .size = sizeof(long), - .align = sizeof(long), - .regset_get = regs_get, - .set = regs_set, - }, -}; - -static const struct user_regset_view user_h8300_native_view = { - .name = "h8300", - .e_machine = EM_H8_300, - .regsets = h8300_regsets, - .n = ARRAY_SIZE(h8300_regsets), -}; - -const struct user_regset_view *task_user_regset_view(struct task_struct *task) -{ - return &user_h8300_native_view; -} - -void ptrace_disable(struct task_struct *child) -{ - user_disable_single_step(child); -} - -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - int ret; - - switch (request) { - default: - ret = ptrace_request(child, request, addr, data); - break; - } - return ret; -} - -asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) -{ - long ret = 0; - - if (test_thread_flag(TIF_SYSCALL_TRACE) && - tracehook_report_syscall_entry(regs)) - /* - * Tracing decided this syscall should not happen. - * We'll return a bogus call number to get an ENOSYS - * error, but leave the original number in regs->regs[0]. - */ - ret = -1L; - - audit_syscall_entry(regs->er1, regs->er2, regs->er3, - regs->er4, regs->er5); - - return ret ?: regs->er0; -} - -asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) -{ - int step; - - audit_syscall_exit(regs); - - step = test_thread_flag(TIF_SINGLESTEP); - if (step || test_thread_flag(TIF_SYSCALL_TRACE)) - tracehook_report_syscall_exit(regs, step); -} diff --git a/arch/h8300/kernel/ptrace_h.c b/arch/h8300/kernel/ptrace_h.c deleted file mode 100644 index 15db45a03b04..000000000000 --- a/arch/h8300/kernel/ptrace_h.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * ptrace cpu depend helper functions - * - * Copyright 2003, 2015 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of - * this archive for more details. - */ - -#include -#include -#include - -#define BREAKINST 0x5730 /* trapa #3 */ - -/* disable singlestep */ -void user_disable_single_step(struct task_struct *child) -{ - if ((long)child->thread.breakinfo.addr != -1L) { - *(child->thread.breakinfo.addr) = child->thread.breakinfo.inst; - child->thread.breakinfo.addr = (unsigned short *)-1L; - } -} - -/* calculate next pc */ -enum jump_type {none, /* normal instruction */ - jabs, /* absolute address jump */ - ind, /* indirect address jump */ - ret, /* return to subrutine */ - reg, /* register indexed jump */ - relb, /* pc relative jump (byte offset) */ - relw, /* pc relative jump (word offset) */ - }; - -/* opcode decode table define - ptn: opcode pattern - msk: opcode bitmask - len: instruction length (<0 next table index) - jmp: jump operation mode */ -struct optable { - unsigned char bitpattern; - unsigned char bitmask; - signed char length; - signed char type; -} __packed __aligned(1); - -#define OPTABLE(ptn, msk, len, jmp) \ - { \ - .bitpattern = ptn, \ - .bitmask = msk, \ - .length = len, \ - .type = jmp, \ - } - -static const struct optable optable_0[] = { - OPTABLE(0x00, 0xff, 1, none), /* 0x00 */ - OPTABLE(0x01, 0xff, -1, none), /* 0x01 */ - OPTABLE(0x02, 0xfe, 1, none), /* 0x02-0x03 */ - OPTABLE(0x04, 0xee, 1, none), /* 0x04-0x05/0x14-0x15 */ - OPTABLE(0x06, 0xfe, 1, none), /* 0x06-0x07 */ - OPTABLE(0x08, 0xea, 1, none), /* 0x08-0x09/0x0c-0x0d/0x18-0x19/0x1c-0x1d */ - OPTABLE(0x0a, 0xee, 1, none), /* 0x0a-0x0b/0x1a-0x1b */ - OPTABLE(0x0e, 0xee, 1, none), /* 0x0e-0x0f/0x1e-0x1f */ - OPTABLE(0x10, 0xfc, 1, none), /* 0x10-0x13 */ - OPTABLE(0x16, 0xfe, 1, none), /* 0x16-0x17 */ - OPTABLE(0x20, 0xe0, 1, none), /* 0x20-0x3f */ - OPTABLE(0x40, 0xf0, 1, relb), /* 0x40-0x4f */ - OPTABLE(0x50, 0xfc, 1, none), /* 0x50-0x53 */ - OPTABLE(0x54, 0xfd, 1, ret), /* 0x54/0x56 */ - OPTABLE(0x55, 0xff, 1, relb), /* 0x55 */ - OPTABLE(0x57, 0xff, 1, none), /* 0x57 */ - OPTABLE(0x58, 0xfb, 2, relw), /* 0x58/0x5c */ - OPTABLE(0x59, 0xfb, 1, reg), /* 0x59/0x5b */ - OPTABLE(0x5a, 0xfb, 2, jabs), /* 0x5a/0x5e */ - OPTABLE(0x5b, 0xfb, 2, ind), /* 0x5b/0x5f */ - OPTABLE(0x60, 0xe8, 1, none), /* 0x60-0x67/0x70-0x77 */ - OPTABLE(0x68, 0xfa, 1, none), /* 0x68-0x69/0x6c-0x6d */ - OPTABLE(0x6a, 0xfe, -2, none), /* 0x6a-0x6b */ - OPTABLE(0x6e, 0xfe, 2, none), /* 0x6e-0x6f */ - OPTABLE(0x78, 0xff, 4, none), /* 0x78 */ - OPTABLE(0x79, 0xff, 2, none), /* 0x79 */ - OPTABLE(0x7a, 0xff, 3, none), /* 0x7a */ - OPTABLE(0x7b, 0xff, 2, none), /* 0x7b */ - OPTABLE(0x7c, 0xfc, 2, none), /* 0x7c-0x7f */ - OPTABLE(0x80, 0x80, 1, none), /* 0x80-0xff */ -}; - -static const struct optable optable_1[] = { - OPTABLE(0x00, 0xff, -3, none), /* 0x0100 */ - OPTABLE(0x40, 0xf0, -3, none), /* 0x0140-0x14f */ - OPTABLE(0x80, 0xf0, 1, none), /* 0x0180-0x018f */ - OPTABLE(0xc0, 0xc0, 2, none), /* 0x01c0-0x01ff */ -}; - -static const struct optable optable_2[] = { - OPTABLE(0x00, 0x20, 2, none), /* 0x6a0?/0x6a8?/0x6b0?/0x6b8? */ - OPTABLE(0x20, 0x20, 3, none), /* 0x6a2?/0x6aa?/0x6b2?/0x6ba? */ -}; - -static const struct optable optable_3[] = { - OPTABLE(0x69, 0xfb, 2, none), /* 0x010069/0x01006d/014069/0x01406d */ - OPTABLE(0x6b, 0xff, -4, none), /* 0x01006b/0x01406b */ - OPTABLE(0x6f, 0xff, 3, none), /* 0x01006f/0x01406f */ - OPTABLE(0x78, 0xff, 5, none), /* 0x010078/0x014078 */ -}; - -static const struct optable optable_4[] = { -/* 0x0100690?/0x01006d0?/0140690?/0x01406d0?/ - 0x0100698?/0x01006d8?/0140698?/0x01406d8? */ - OPTABLE(0x00, 0x78, 3, none), -/* 0x0100692?/0x01006d2?/0140692?/0x01406d2?/ - 0x010069a?/0x01006da?/014069a?/0x01406da? */ - OPTABLE(0x20, 0x78, 4, none), -}; - -static const struct optables_list { - const struct optable *ptr; - int size; -} optables[] = { -#define OPTABLES(no) \ - { \ - .ptr = optable_##no, \ - .size = sizeof(optable_##no) / sizeof(struct optable), \ - } - OPTABLES(0), - OPTABLES(1), - OPTABLES(2), - OPTABLES(3), - OPTABLES(4), - -}; - -const unsigned char condmask[] = { - 0x00, 0x40, 0x01, 0x04, 0x02, 0x08, 0x10, 0x20 -}; - -static int isbranch(struct task_struct *task, int reson) -{ - unsigned char cond = h8300_get_reg(task, PT_CCR); - - /* encode complex conditions */ - /* B4: N^V - B5: Z|(N^V) - B6: C|Z */ - __asm__("bld #3,%w0\n\t" - "bxor #1,%w0\n\t" - "bst #4,%w0\n\t" - "bor #2,%w0\n\t" - "bst #5,%w0\n\t" - "bld #2,%w0\n\t" - "bor #0,%w0\n\t" - "bst #6,%w0\n\t" - : "=&r"(cond) : "0"(cond) : "cc"); - cond &= condmask[reson >> 1]; - if (!(reson & 1)) - return cond == 0; - else - return cond != 0; -} - -static unsigned short *decode(struct task_struct *child, - const struct optable *op, - char *fetch_p, unsigned short *pc, - unsigned char inst) -{ - unsigned long addr; - unsigned long *sp; - int regno; - - switch (op->type) { - case none: - return (unsigned short *)pc + op->length; - case jabs: - addr = *(unsigned long *)pc; - return (unsigned short *)(addr & 0x00ffffff); - case ind: - addr = *pc & 0xff; - return (unsigned short *)(*(unsigned long *)addr); - case ret: - sp = (unsigned long *)h8300_get_reg(child, PT_USP); - /* user stack frames - | er0 | temporary saved - +--------+ - | exp | exception stack frames - +--------+ - | ret pc | userspace return address - */ - return (unsigned short *)(*(sp+2) & 0x00ffffff); - case reg: - regno = (*pc >> 4) & 0x07; - if (regno == 0) - addr = h8300_get_reg(child, PT_ER0); - else - addr = h8300_get_reg(child, regno-1 + PT_ER1); - return (unsigned short *)addr; - case relb: - if (inst == 0x55 || isbranch(child, inst & 0x0f)) - pc = (unsigned short *)((unsigned long)pc + - ((signed char)(*fetch_p))); - return pc+1; /* skip myself */ - case relw: - if (inst == 0x5c || isbranch(child, (*fetch_p & 0xf0) >> 4)) - pc = (unsigned short *)((unsigned long)pc + - ((signed short)(*(pc+1)))); - return pc+2; /* skip myself */ - default: - return NULL; - } -} - -static unsigned short *nextpc(struct task_struct *child, unsigned short *pc) -{ - const struct optable *op; - unsigned char *fetch_p; - int op_len; - unsigned char inst; - - op = optables[0].ptr; - op_len = optables[0].size; - fetch_p = (unsigned char *)pc; - inst = *fetch_p++; - do { - if ((inst & op->bitmask) == op->bitpattern) { - if (op->length < 0) { - op = optables[-op->length].ptr; - op_len = optables[-op->length].size + 1; - inst = *fetch_p++; - } else - return decode(child, op, fetch_p, pc, inst); - } else - op++; - } while (--op_len > 0); - return NULL; -} - -/* Set breakpoint(s) to simulate a single step from the current PC. */ - -void user_enable_single_step(struct task_struct *child) -{ - unsigned short *next; - - next = nextpc(child, (unsigned short *)h8300_get_reg(child, PT_PC)); - child->thread.breakinfo.addr = next; - child->thread.breakinfo.inst = *next; - *next = BREAKINST; -} - -asmlinkage void trace_trap(unsigned long bp) -{ - if ((unsigned long)current->thread.breakinfo.addr == bp) { - user_disable_single_step(current); - force_sig(SIGTRAP); - } else - force_sig(SIGILL); -} diff --git a/arch/h8300/kernel/ptrace_s.c b/arch/h8300/kernel/ptrace_s.c deleted file mode 100644 index ee21f37b7ed4..000000000000 --- a/arch/h8300/kernel/ptrace_s.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * linux/arch/h8300/kernel/ptrace_h8s.c - * ptrace cpu depend helper functions - * - * Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of - * this archive for more details. - */ - -#include -#include -#include -#include - -#define CCR_MASK 0x6f -#define EXR_TRACE 0x80 - -/* disable singlestep */ -void user_disable_single_step(struct task_struct *child) -{ - unsigned char exr; - - exr = h8300_get_reg(child, PT_EXR); - exr &= ~EXR_TRACE; - h8300_put_reg(child, PT_EXR, exr); -} - -/* enable singlestep */ -void user_enable_single_step(struct task_struct *child) -{ - unsigned char exr; - - exr = h8300_get_reg(child, PT_EXR); - exr |= EXR_TRACE; - h8300_put_reg(child, PT_EXR, exr); -} - -asmlinkage void trace_trap(unsigned long bp) -{ - (void)bp; - force_sig(SIGTRAP); -} diff --git a/arch/h8300/kernel/setup.c b/arch/h8300/kernel/setup.c deleted file mode 100644 index 61091a76eb7e..000000000000 --- a/arch/h8300/kernel/setup.c +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/kernel/setup.c - * - * Copyright (C) 2001-2014 Yoshinori Sato - */ - -/* - * This file handles the architecture-dependent parts of system setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#if defined(CONFIG_CPU_H8300H) -#define CPU "H8/300H" -#elif defined(CONFIG_CPU_H8S) -#define CPU "H8S" -#else -#define CPU "Unknown" -#endif - -unsigned long memory_start; -unsigned long memory_end; -EXPORT_SYMBOL(memory_end); -static unsigned long freq; -extern char __dtb_start[]; - -#ifdef CONFIG_VT -struct screen_info screen_info; -#endif - -char __initdata command_line[COMMAND_LINE_SIZE]; - -void sim_console_register(void); - -void __init h8300_fdt_init(void *fdt, char *bootargs) -{ - if (!fdt) - fdt = __dtb_start; - else - strcpy(command_line, bootargs); - - early_init_dt_scan(fdt); - memblock_allow_resize(); -} - -static void __init bootmem_init(void) -{ - memory_end = memory_start = 0; - - /* Find main memory where is the kernel */ - memory_start = memblock_start_of_DRAM(); - memory_end = memblock_end_of_DRAM(); - - if (!memory_end) - panic("No memory!"); - - /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */ - min_low_pfn = PFN_UP(memory_start); - max_low_pfn = PFN_DOWN(memory_end); - max_pfn = max_low_pfn; - - memblock_reserve(__pa(_stext), _end - _stext); - - early_init_fdt_reserve_self(); - early_init_fdt_scan_reserved_mem(); - - memblock_dump_all(); -} - -void __init setup_arch(char **cmdline_p) -{ - unflatten_and_copy_device_tree(); - - setup_initial_init_mm(_stext, _etext, _edata, NULL); - - pr_notice("\r\n\nuClinux " CPU "\n"); - pr_notice("Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n"); - - if (*command_line) - strcpy(boot_command_line, command_line); - *cmdline_p = boot_command_line; - - parse_early_param(); - - bootmem_init(); - /* - * get kmalloc into gear - */ - paging_init(); -} - -/* - * Get CPU information for use by the procfs. - */ - -static int show_cpuinfo(struct seq_file *m, void *v) -{ - char *cpu; - - cpu = CPU; - - seq_printf(m, "CPU:\t\t%s\n" - "Clock:\t\t%lu.%1luMHz\n" - "BogoMips:\t%lu.%02lu\n" - "Calibration:\t%lu loops\n", - cpu, - freq/1000, freq%1000, - (loops_per_jiffy*HZ)/500000, - ((loops_per_jiffy*HZ)/5000)%100, - (loops_per_jiffy*HZ)); - - return 0; -} - -static void *c_start(struct seq_file *m, loff_t *pos) -{ - return *pos < num_possible_cpus() ? - ((void *) 0x12345678) : NULL; -} - -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return c_start(m, pos); -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -const struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; - -#if defined(CONFIG_CPU_H8300H) -#define get_wait(base, addr) ({ \ - int baddr; \ - baddr = ((addr) / 0x200000 * 2); \ - w *= (readw((base) + 2) & (3 << baddr)) + 1; \ - }) -#endif -#if defined(CONFIG_CPU_H8S) -#define get_wait(base, addr) ({ \ - int baddr; \ - baddr = ((addr) / 0x200000 * 16); \ - w *= (readl((base) + 2) & (7 << baddr)) + 1; \ - }) -#endif - -static __init int access_timing(void) -{ - struct device_node *bsc; - void __iomem *base; - unsigned long addr = (unsigned long)&__delay; - int bit = 1 << (addr / 0x200000); - int w; - - bsc = of_find_compatible_node(NULL, NULL, "renesas,h8300-bsc"); - base = of_iomap(bsc, 0); - w = (readb(base + 0) & bit)?2:1; - if (readb(base + 1) & bit) - w *= get_wait(base, addr); - else - w *= 2; - return w * 3 / 2; -} - -void __init calibrate_delay(void) -{ - struct device_node *cpu; - int freq; - - cpu = of_find_compatible_node(NULL, NULL, "renesas,h8300"); - of_property_read_s32(cpu, "clock-frequency", &freq); - loops_per_jiffy = freq / HZ / (access_timing() * 2); - pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", - loops_per_jiffy / (500000 / HZ), - (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); -} - - -void __init time_init(void) -{ - of_clk_init(NULL); - timer_probe(); -} diff --git a/arch/h8300/kernel/signal.c b/arch/h8300/kernel/signal.c deleted file mode 100644 index 75a1c36b105a..000000000000 --- a/arch/h8300/kernel/signal.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * linux/arch/h8300/kernel/signal.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * uClinux H8/300 support by Yoshinori Sato - * and David McCullough - * - * Based on - * Linux/m68k by Hamish Macdonald - */ - -/* - * ++roman (07/09/96): implemented signal stacks (specially for tosemu on - * Atari :-) Current limitation: Only one sigstack can be active at one time. - * If a second signal with SA_ONSTACK set arrives while working on a sigstack, - * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested - * signal handlers! - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * Do a signal return; undo the signal stack. - * - * Keep the return code on the stack quadword aligned! - * That makes the cache flush below easier. - */ - -struct rt_sigframe { - long dummy_er0; - long dummy_vector; -#if defined(CONFIG_CPU_H8S) - short dummy_exr; -#endif - long dummy_pc; - char *pretcode; - struct siginfo *pinfo; - void *puc; - unsigned char retcode[8]; - struct siginfo info; - struct ucontext uc; - int sig; -} __packed __aligned(2); - -static inline int -restore_sigcontext(struct sigcontext *usc, int *pd0) -{ - struct pt_regs *regs = current_pt_regs(); - int err = 0; - unsigned int ccr; - unsigned int usp; - unsigned int er0; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - - /* restore passed registers */ -#define COPY(r) do { err |= get_user(regs->r, &usc->sc_##r); } while (0) - COPY(er1); - COPY(er2); - COPY(er3); - COPY(er5); - COPY(pc); - ccr = regs->ccr & 0x10; - COPY(ccr); -#undef COPY - regs->ccr &= 0xef; - regs->ccr |= ccr; - regs->orig_er0 = -1; /* disable syscall checks */ - err |= __get_user(usp, &usc->sc_usp); - regs->sp = usp; - - err |= __get_user(er0, &usc->sc_er0); - *pd0 = er0; - return err; -} - -asmlinkage int sys_rt_sigreturn(void) -{ - unsigned long usp = rdusp(); - struct rt_sigframe *frame = (struct rt_sigframe *)(usp - 4); - sigset_t set; - int er0; - - if (!access_ok(frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(&frame->uc.uc_mcontext, &er0)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - return er0; - -badframe: - force_sig(SIGSEGV); - return 0; -} - -static int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, - unsigned long mask) -{ - int err = 0; - - err |= __put_user(regs->er0, &sc->sc_er0); - err |= __put_user(regs->er1, &sc->sc_er1); - err |= __put_user(regs->er2, &sc->sc_er2); - err |= __put_user(regs->er3, &sc->sc_er3); - err |= __put_user(regs->er4, &sc->sc_er4); - err |= __put_user(regs->er5, &sc->sc_er5); - err |= __put_user(regs->er6, &sc->sc_er6); - err |= __put_user(rdusp(), &sc->sc_usp); - err |= __put_user(regs->pc, &sc->sc_pc); - err |= __put_user(regs->ccr, &sc->sc_ccr); - err |= __put_user(mask, &sc->sc_mask); - - return err; -} - -static inline void __user * -get_sigframe(struct ksignal *ksig, struct pt_regs *regs, size_t frame_size) -{ - return (void __user *)((sigsp(rdusp(), ksig) - frame_size) & -8UL); -} - -static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, - struct pt_regs *regs) -{ - struct rt_sigframe *frame; - int err = 0; - unsigned char *ret; - - frame = get_sigframe(ksig, regs, sizeof(*frame)); - - if (!access_ok(frame, sizeof(*frame))) - return -EFAULT; - - if (ksig->ka.sa.sa_flags & SA_SIGINFO) - err |= copy_siginfo_to_user(&frame->info, &ksig->info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __save_altstack(&frame->uc.uc_stack, rdusp()); - err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); - err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - if (err) - return -EFAULT; - - /* Set up to return from userspace. */ - ret = (unsigned char *)&frame->retcode; - if (ksig->ka.sa.sa_flags & SA_RESTORER) - ret = (unsigned char *)(ksig->ka.sa.sa_restorer); - else { - /* sub.l er0,er0; mov.b #__NR_rt_sigreturn,r0l; trapa #0 */ - err |= __put_user(0x1a80f800 + (__NR_rt_sigreturn & 0xff), - (unsigned long *)(frame->retcode + 0)); - err |= __put_user(0x5700, - (unsigned short *)(frame->retcode + 4)); - } - err |= __put_user(ret, &frame->pretcode); - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - regs->sp = (unsigned long)frame; - regs->pc = (unsigned long)ksig->ka.sa.sa_handler; - regs->er0 = ksig->sig; - regs->er1 = (unsigned long)&(frame->info); - regs->er2 = (unsigned long)&frame->uc; - regs->er5 = current->mm->start_data; /* GOT base */ - - return 0; -} - -static void -handle_restart(struct pt_regs *regs, struct k_sigaction *ka) -{ - switch (regs->er0) { - case -ERESTARTNOHAND: - if (!ka) - goto do_restart; - regs->er0 = -EINTR; - break; - case -ERESTART_RESTARTBLOCK: - if (!ka) { - regs->er0 = __NR_restart_syscall; - regs->pc -= 2; - } else - regs->er0 = -EINTR; - break; - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->er0 = -EINTR; - break; - } - fallthrough; - case -ERESTARTNOINTR: -do_restart: - regs->er0 = regs->orig_er0; - regs->pc -= 2; - break; - } -} - -/* - * OK, we're invoking a handler - */ -static void -handle_signal(struct ksignal *ksig, struct pt_regs *regs) -{ - sigset_t *oldset = sigmask_to_save(); - int ret; - /* are we from a system call? */ - if (regs->orig_er0 >= 0) - handle_restart(regs, &ksig->ka); - - ret = setup_rt_frame(ksig, oldset, regs); - - signal_setup_done(ret, ksig, 0); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -static void do_signal(struct pt_regs *regs) -{ - struct ksignal ksig; - - current->thread.esp0 = (unsigned long) regs; - - if (get_signal(&ksig)) { - /* Whee! Actually deliver the signal. */ - handle_signal(&ksig, regs); - return; - } - /* Did we come from a system call? */ - if (regs->orig_er0 >= 0) - handle_restart(regs, NULL); - - /* If there's no signal to deliver, we just restore the saved mask. */ - restore_saved_sigmask(); -} - -asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags) -{ - if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL)) - do_signal(regs); - - if (thread_info_flags & _TIF_NOTIFY_RESUME) - tracehook_notify_resume(regs); -} diff --git a/arch/h8300/kernel/sim-console.c b/arch/h8300/kernel/sim-console.c deleted file mode 100644 index 03aa35b1a08c..000000000000 --- a/arch/h8300/kernel/sim-console.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/h8300/kernel/sim-console.c - * - * Copyright (C) 2015 Yoshinori Sato - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include - -static void sim_write(struct console *con, const char *s, unsigned n) -{ - register const char *_ptr __asm__("er1") = s; - register const unsigned _len __asm__("er2") = n; - - __asm__("sub.l er0,er0\n\t" /* er0 = 1 (stdout) */ - "inc.l #1,er0\n\t" - ".byte 0x5e,0x00,0x00,0xc7\n\t" /* jsr @0xc7 (sys_write) */ - : : "g"(_ptr), "g"(_len):"er0"); -} - -static int __init sim_setup(struct earlycon_device *device, const char *opt) -{ - device->con->write = sim_write; - return 0; -} - -EARLYCON_DECLARE(h8sim, sim_setup); diff --git a/arch/h8300/kernel/syscalls.c b/arch/h8300/kernel/syscalls.c deleted file mode 100644 index 9022036fb3d2..000000000000 --- a/arch/h8300/kernel/syscalls.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -#undef __SYSCALL -#define __SYSCALL(nr, call) [nr] = (call), - -#define sys_mmap2 sys_mmap_pgoff - -asmlinkage int sys_rt_sigreturn(void); - -void *_sys_call_table[__NR_syscalls] = { -#include -}; diff --git a/arch/h8300/kernel/traps.c b/arch/h8300/kernel/traps.c deleted file mode 100644 index a92c39e03802..000000000000 --- a/arch/h8300/kernel/traps.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * linux/arch/h8300/boot/traps.c -- general exception handling code - * H8/300 support Yoshinori Sato - * - * Cloned from Linux/m68k. - * - * No original Copyright holder listed, - * Probable original (C) Roman Zippel (assigned DJD, 1999) - * - * Copyright 1999-2000 D. Jeff Dionne, - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static DEFINE_SPINLOCK(die_lock); - -/* - * this must be called very early as the kernel might - * use some instruction that are emulated on the 060 - */ - -void __init base_trap_init(void) -{ -} - -asmlinkage void set_esp0(unsigned long ssp) -{ - current->thread.esp0 = ssp; -} - -/* - * Generic dumping code. Used for panic and debug. - */ - -static void dump(struct pt_regs *fp) -{ - unsigned long *sp; - unsigned char *tp; - int i; - - pr_info("\nCURRENT PROCESS:\n\n"); - pr_info("COMM=%s PID=%d\n", current->comm, current->pid); - if (current->mm) { - pr_info("TEXT=%08x-%08x DATA=%08x-%08x BSS=%08x-%08x\n", - (int) current->mm->start_code, - (int) current->mm->end_code, - (int) current->mm->start_data, - (int) current->mm->end_data, - (int) current->mm->end_data, - (int) current->mm->brk); - pr_info("USER-STACK=%08x KERNEL-STACK=%08lx\n\n", - (int) current->mm->start_stack, - (int) PAGE_SIZE+(unsigned long)current); - } - - show_regs(fp); - pr_info("\nCODE:"); - tp = ((unsigned char *) fp->pc) - 0x20; - for (sp = (unsigned long *) tp, i = 0; (i < 0x40); i += 4) { - if ((i % 0x10) == 0) - pr_info("\n%08x: ", (int) (tp + i)); - pr_info("%08x ", (int) *sp++); - } - pr_info("\n"); - - pr_info("\nKERNEL STACK:"); - tp = ((unsigned char *) fp) - 0x40; - for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) { - if ((i % 0x10) == 0) - pr_info("\n%08x: ", (int) (tp + i)); - pr_info("%08x ", (int) *sp++); - } - pr_info("\n"); - if (STACK_MAGIC != *(unsigned long *)((unsigned long)current+PAGE_SIZE)) - pr_info("(Possibly corrupted stack page??)\n"); - - pr_info("\n\n"); -} - -void die(const char *str, struct pt_regs *fp, unsigned long err) -{ - static int diecount; - - oops_enter(); - - console_verbose(); - spin_lock_irq(&die_lock); - report_bug(fp->pc, fp); - pr_crit("%s: %04lx [#%d] ", str, err & 0xffff, ++diecount); - dump(fp); - - spin_unlock_irq(&die_lock); - make_task_dead(SIGSEGV); -} - -static int kstack_depth_to_print = 24; - -void show_stack(struct task_struct *task, unsigned long *esp, const char *loglvl) -{ - unsigned long *stack, addr; - int i; - - if (esp == NULL) - esp = (unsigned long *) &esp; - - stack = esp; - - printk("%sStack from %08lx:", loglvl, (unsigned long)stack); - for (i = 0; i < kstack_depth_to_print; i++) { - if (((unsigned long)stack & (THREAD_SIZE - 1)) >= - THREAD_SIZE-4) - break; - if (i % 8 == 0) - printk("%s ", loglvl); - pr_cont(" %08lx", *stack++); - } - - printk("%s\nCall Trace:\n", loglvl); - i = 0; - stack = esp; - while (((unsigned long)stack & (THREAD_SIZE - 1)) < THREAD_SIZE-4) { - addr = *stack++; - /* - * If the address is either in the text segment of the - * kernel, or in the region which contains vmalloc'ed - * memory, it *may* be the address of a calling - * routine; if so, print it so that someone tracing - * down the cause of the crash will be able to figure - * out the call path that was taken. - */ - if (check_kernel_text(addr)) { - if (i % 4 == 0) - printk("%s ", loglvl); - pr_cont(" [<%08lx>]", addr); - i++; - } - } - printk("%s\n", loglvl); -} diff --git a/arch/h8300/kernel/vmlinux.lds.S b/arch/h8300/kernel/vmlinux.lds.S deleted file mode 100644 index 6b1afc2f9b68..000000000000 --- a/arch/h8300/kernel/vmlinux.lds.S +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#define RO_EXCEPTION_TABLE_ALIGN 16 - -#include -#include -#include - -#define ROMTOP 0x000000 -#define RAMTOP 0x400000 - -jiffies = jiffies_64 + 4; - -ENTRY(_start) - -SECTIONS -{ -#if defined(CONFIG_ROMKERNEL) - . = ROMTOP; - .vectors : - { - _vector = . ; - *(.vector*) - } -#else - . = RAMTOP; - _ramstart = .; - . = . + CONFIG_OFFSET; -#endif - _text = .; - HEAD_TEXT_SECTION - .text : { - _stext = . ; - TEXT_TEXT - SCHED_TEXT - CPUIDLE_TEXT - LOCK_TEXT -#if defined(CONFIG_ROMKERNEL) - *(.int_redirect) -#endif - _etext = . ; - } - RO_DATA(4) - ROMEND = .; -#if defined(CONFIG_ROMKERNEL) - . = RAMTOP; - _ramstart = .; -#define ADDR(x) ROMEND -#endif - _sdata = . ; - __data_start = . ; - RW_DATA(0, PAGE_SIZE, THREAD_SIZE) -#if defined(CONFIG_ROMKERNEL) -#undef ADDR -#endif - . = ALIGN(0x4) ; - __init_begin = .; - INIT_TEXT_SECTION(4) - INIT_DATA_SECTION(4) - __init_end = .; - _edata = . ; - _begin_data = LOADADDR(.data); - _sbss =.; - BSS_SECTION(0, 0 ,0) - _ebss =.; - _ramend = .; - _end = .; - DISCARDS -} diff --git a/arch/h8300/lib/Makefile b/arch/h8300/lib/Makefile deleted file mode 100644 index 5911c1fa856d..000000000000 --- a/arch/h8300/lib/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for H8/300-specific library files.. -# - -lib-y = memcpy.o memset.o abs.o \ - mulsi3.o udivsi3.o muldi3.o moddivsi3.o \ - ashldi3.o lshrdi3.o ashrdi3.o ucmpdi2.o \ - delay.o diff --git a/arch/h8300/lib/abs.S b/arch/h8300/lib/abs.S deleted file mode 100644 index 6e1a4ed3af53..000000000000 --- a/arch/h8300/lib/abs.S +++ /dev/null @@ -1,21 +0,0 @@ -;;; SPDX-License-Identifier: GPL-2.0 -;;; abs.S - -#include - -#if defined(CONFIG_CPU_H8300H) - .h8300h -#endif -#if defined(CONFIG_CPU_H8S) - .h8300s -#endif - .text -.global _abs - -;;; int abs(int n) -_abs: - mov.l er0,er0 - bpl 1f - neg.l er0 -1: - rts diff --git a/arch/h8300/lib/ashldi3.c b/arch/h8300/lib/ashldi3.c deleted file mode 100644 index 430720c0c5d8..000000000000 --- a/arch/h8300/lib/ashldi3.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "libgcc.h" - -DWtype -__ashldi3(DWtype u, word_type b) -{ - const DWunion uu = {.ll = u}; - const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; - DWunion w; - - if (b == 0) - return u; - - if (bm <= 0) { - w.s.low = 0; - w.s.high = (UWtype) uu.s.low << -bm; - } else { - const UWtype carries = (UWtype) uu.s.low >> bm; - - w.s.low = (UWtype) uu.s.low << b; - w.s.high = ((UWtype) uu.s.high << b) | carries; - } - - return w.ll; -} diff --git a/arch/h8300/lib/ashrdi3.c b/arch/h8300/lib/ashrdi3.c deleted file mode 100644 index 2c6cd424eb3e..000000000000 --- a/arch/h8300/lib/ashrdi3.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "libgcc.h" - -DWtype __ashrdi3(DWtype u, word_type b) -{ - const DWunion uu = {.ll = u}; - const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; - DWunion w; - - if (b == 0) - return u; - - if (bm <= 0) { - /* w.s.high = 1..1 or 0..0 */ - w.s.high = uu.s.high >> (sizeof (Wtype) * BITS_PER_UNIT - 1); - w.s.low = uu.s.high >> -bm; - } else { - const UWtype carries = (UWtype) uu.s.high << bm; - - w.s.high = uu.s.high >> b; - w.s.low = ((UWtype) uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/h8300/lib/delay.c b/arch/h8300/lib/delay.c deleted file mode 100644 index f4277529a9b9..000000000000 --- a/arch/h8300/lib/delay.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * delay loops - * - * Copyright (C) 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include - -void __delay(unsigned long cycles) -{ - __asm__ volatile ("1: dec.l #1,%0\n\t" - "bne 1b":"=r"(cycles):"0"(cycles)); -} -EXPORT_SYMBOL(__delay); - -void __const_udelay(unsigned long xloops) -{ - u64 loops; - - loops = (u64)xloops * loops_per_jiffy * HZ; - - __delay(loops >> 32); -} -EXPORT_SYMBOL(__const_udelay); - -void __udelay(unsigned long usecs) -{ - __const_udelay(usecs * 0x10C7UL); /* 2**32 / 1000000 (rounded up) */ -} -EXPORT_SYMBOL(__udelay); - -void __ndelay(unsigned long nsecs) -{ - __const_udelay(nsecs * 0x5UL); /* 2**32 / 1000000000 (rounded up) */ -} -EXPORT_SYMBOL(__ndelay); diff --git a/arch/h8300/lib/libgcc.h b/arch/h8300/lib/libgcc.h deleted file mode 100644 index b8bcf7035ff5..000000000000 --- a/arch/h8300/lib/libgcc.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __H8300_LIBGCC_H__ -#define __H8300_LIBGCC_H__ - -#ifdef __ASSEMBLY__ -#define A0 r0 -#define A0L r0l -#define A0H r0h - -#define A1 r1 -#define A1L r1l -#define A1H r1h - -#define A2 r2 -#define A2L r2l -#define A2H r2h - -#define A3 r3 -#define A3L r3l -#define A3H r3h - -#define S0 r4 -#define S0L r4l -#define S0H r4h - -#define S1 r5 -#define S1L r5l -#define S1H r5h - -#define S2 r6 -#define S2L r6l -#define S2H r6h - -#define PUSHP push.l -#define POPP pop.l - -#define A0P er0 -#define A1P er1 -#define A2P er2 -#define A3P er3 -#define S0P er4 -#define S1P er5 -#define S2P er6 - -#define A0E e0 -#define A1E e1 -#define A2E e2 -#define A3E e3 -#else -#define Wtype SItype -#define UWtype USItype -#define HWtype SItype -#define UHWtype USItype -#define DWtype DItype -#define UDWtype UDItype -#define UWtype USItype -#define Wtype SItype -#define UWtype USItype -#define W_TYPE_SIZE (4 * BITS_PER_UNIT) -#define BITS_PER_UNIT (8) - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); -typedef int DItype __attribute__ ((mode (DI))); -typedef unsigned int UDItype __attribute__ ((mode (DI))); -struct DWstruct { - Wtype high, low; -}; -typedef union { - struct DWstruct s; - DWtype ll; -} DWunion; - -typedef int word_type __attribute__ ((mode (__word__))); - -#endif - -#endif diff --git a/arch/h8300/lib/lshrdi3.c b/arch/h8300/lib/lshrdi3.c deleted file mode 100644 index 8dbc861ca589..000000000000 --- a/arch/h8300/lib/lshrdi3.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "libgcc.h" - -DWtype __lshrdi3(DWtype u, word_type b) -{ - const DWunion uu = {.ll = u}; - const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; - DWunion w; - - if (b == 0) - return u; - - if (bm <= 0) { - w.s.high = 0; - w.s.low = (UWtype) uu.s.high >> -bm; - } else { - const UWtype carries = (UWtype) uu.s.high << bm; - - w.s.high = (UWtype) uu.s.high >> b; - w.s.low = ((UWtype) uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/h8300/lib/memcpy.S b/arch/h8300/lib/memcpy.S deleted file mode 100644 index f1cd67d5e3ea..000000000000 --- a/arch/h8300/lib/memcpy.S +++ /dev/null @@ -1,86 +0,0 @@ -;;; SPDX-License-Identifier: GPL-2.0 -;;; memcpy.S - -#include - -#if defined(CONFIG_CPU_H8300H) - .h8300h -#endif -#if defined(CONFIG_CPU_H8S) - .h8300s -#endif - .text -.global memcpy - -;;; void *memcpy(void *to, void *from, size_t n) -memcpy: - mov.l er2,er2 - bne 1f - rts -1: - ;; address check - bld #0,r0l - bxor #0,r1l - bcs 4f - mov.l er4,@-sp - mov.l er0,@-sp - btst #0,r0l - beq 1f - ;; (aligned even) odd address - mov.b @er1,r3l - mov.b r3l,@er0 - adds #1,er1 - adds #1,er0 - dec.l #1,er2 - beq 3f -1: - ;; n < sizeof(unsigned long) check - sub.l er4,er4 - adds #4,er4 ; loop count check value - cmp.l er4,er2 - blo 2f - ;; unsigned long copy -1: - mov.l @er1,er3 - mov.l er3,@er0 - adds #4,er0 - adds #4,er1 - subs #4,er2 - cmp.l er4,er2 - bcc 1b - ;; rest -2: - mov.l er2,er2 - beq 3f -1: - mov.b @er1,r3l - mov.b r3l,@er0 - adds #1,er1 - adds #1,er0 - dec.l #1,er2 - bne 1b -3: - mov.l @sp+,er0 - mov.l @sp+,er4 - rts - - ;; odd <- even / even <- odd -4: - mov.l er4,er3 - mov.l er2,er4 - mov.l er5,er2 - mov.l er1,er5 - mov.l er6,er1 - mov.l er0,er6 -1: - eepmov.w - mov.w r4,r4 - bne 1b - dec.w #1,e4 - bpl 1b - mov.l er1,er6 - mov.l er2,er5 - mov.l er3,er4 - rts - - .end diff --git a/arch/h8300/lib/memset.S b/arch/h8300/lib/memset.S deleted file mode 100644 index 2d1abc37fd08..000000000000 --- a/arch/h8300/lib/memset.S +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* memset.S */ - -#include - -#if defined(CONFIG_CPU_H8300H) - .h8300h -#endif -#if defined(CONFIG_CPU_H8S) - .h8300s -#endif - .text - -.global memset -.global clear_user - -;;void *memset(*ptr, int c, size_t count) -;; ptr = er0 -;; c = er1(r1l) -;; count = er2 -memset: - btst #0,r0l - beq 2f - - ;; odd address -1: - mov.b r1l,@er0 - adds #1,er0 - dec.l #1,er2 - beq 6f - - ;; even address -2: - mov.l er2,er3 - cmp.l #4,er2 - blo 4f - ;; count>=4 -> count/4 -#if defined(CONFIG_CPU_H8300H) - shlr.l er2 - shlr.l er2 -#endif -#if defined(CONFIG_CPU_H8S) - shlr.l #2,er2 -#endif - ;; byte -> long - mov.b r1l,r1h - mov.w r1,e1 -3: - mov.l er1,@er0 - adds #4,er0 - dec.l #1,er2 - bne 3b -4: - ;; count % 4 - and.b #3,r3l - beq 6f -5: - mov.b r1l,@er0 - adds #1,er0 - dec.b r3l - bne 5b -6: - rts - -clear_user: - mov.l er1, er2 - sub.l er1, er1 - bra memset - - .end diff --git a/arch/h8300/lib/moddivsi3.S b/arch/h8300/lib/moddivsi3.S deleted file mode 100644 index 9e33ab0456c7..000000000000 --- a/arch/h8300/lib/moddivsi3.S +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include "libgcc.h" - -; numerator in A0/A1 -; denominator in A2/A3 - .global __modsi3 -__modsi3: - PUSHP S2P - bsr modnorm - bsr __divsi3 - mov.l er3,er0 - bra exitdiv - - .global __umodsi3 -__umodsi3: - bsr __udivsi3:16 - mov.l er3,er0 - rts - - .global __divsi3 -__divsi3: - PUSHP S2P - bsr divnorm - bsr __udivsi3:16 - - ; examine what the sign should be -exitdiv: - btst #3,S2L - beq reti - - ; should be -ve - neg.l A0P - -reti: - POPP S2P - rts - -divnorm: - mov.l A0P,A0P ; is the numerator -ve - stc ccr,S2L ; keep the sign in bit 3 of S2L - bge postive - - neg.l A0P ; negate arg - -postive: - mov.l A1P,A1P ; is the denominator -ve - bge postive2 - - neg.l A1P ; negate arg - xor.b #0x08,S2L ; toggle the result sign - -postive2: - rts - -;; Basically the same, except that the sign of the divisor determines -;; the sign. -modnorm: - mov.l A0P,A0P ; is the numerator -ve - stc ccr,S2L ; keep the sign in bit 3 of S2L - bge mpostive - - neg.l A0P ; negate arg - -mpostive: - mov.l A1P,A1P ; is the denominator -ve - bge mpostive2 - - neg.l A1P ; negate arg - -mpostive2: - rts - - .end diff --git a/arch/h8300/lib/modsi3.S b/arch/h8300/lib/modsi3.S deleted file mode 100644 index bdc8a002921d..000000000000 --- a/arch/h8300/lib/modsi3.S +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include "libgcc.h" - -; numerator in A0/A1 -; denominator in A2/A3 - .global __modsi3 -__modsi3: - PUSHP S2P - bsr modnorm - bsr __divsi3 - mov.l er3,er0 - bra exitdiv - - .global __umodsi3 -__umodsi3: - bsr __udivsi3 - mov.l er3,er0 - rts - - .global __divsi3 -__divsi3: - PUSHP S2P - jsr divnorm - bsr __udivsi3 - - ; examine what the sign should be -exitdiv: - btst #3,S2L - beq reti - - ; should be -ve - neg.l A0P - -reti: - POPP S2P - rts - -divnorm: - mov.l A0P,A0P ; is the numerator -ve - stc ccr,S2L ; keep the sign in bit 3 of S2L - bge postive - - neg.l A0P ; negate arg - -postive: - mov.l A1P,A1P ; is the denominator -ve - bge postive2 - - neg.l A1P ; negate arg - xor.b #0x08,S2L ; toggle the result sign - -postive2: - rts - -;; Basically the same, except that the sign of the divisor determines -;; the sign. -modnorm: - mov.l A0P,A0P ; is the numerator -ve - stc ccr,S2L ; keep the sign in bit 3 of S2L - bge mpostive - - neg.l A0P ; negate arg - -mpostive: - mov.l A1P,A1P ; is the denominator -ve - bge mpostive2 - - neg.l A1P ; negate arg - -mpostive2: - rts - - .end diff --git a/arch/h8300/lib/muldi3.c b/arch/h8300/lib/muldi3.c deleted file mode 100644 index 9cb11b134e54..000000000000 --- a/arch/h8300/lib/muldi3.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "libgcc.h" - -#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) -#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) -#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) - -#define umul_ppmm(w1, w0, u, v) \ - do { \ - UWtype __x0, __x1, __x2, __x3; \ - UHWtype __ul, __vl, __uh, __vh; \ - __ul = __ll_lowpart(u); \ - __uh = __ll_highpart(u); \ - __vl = __ll_lowpart(v); \ - __vh = __ll_highpart(v); \ - __x0 = (UWtype) __ul * __vl; \ - __x1 = (UWtype) __ul * __vh; \ - __x2 = (UWtype) __uh * __vl; \ - __x3 = (UWtype) __uh * __vh; \ - __x1 += __ll_highpart(__x0); \ - __x1 += __x2; \ - if (__x1 < __x2) \ - __x3 += __ll_B; \ - (w1) = __x3 + __ll_highpart(__x1); \ - (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0); \ - } while (0) - -#define __umulsidi3(u, v) ( \ - { \ - DWunion __w; \ - umul_ppmm(__w.s.high, __w.s.low, u, v); \ - __w.ll; } \ - ) - -DWtype __muldi3(DWtype u, DWtype v) -{ - const DWunion uu = {.ll = u}; - const DWunion vv = {.ll = v}; - DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)}; - - w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high - + (UWtype) uu.s.high * (UWtype) vv.s.low); - - return w.ll; -} diff --git a/arch/h8300/lib/mulsi3.S b/arch/h8300/lib/mulsi3.S deleted file mode 100644 index 5a062fd298d1..000000000000 --- a/arch/h8300/lib/mulsi3.S +++ /dev/null @@ -1,39 +0,0 @@ -; SPDX-License-Identifier: GPL-2.0 -; -; mulsi3 for H8/300H - based on Renesas SH implementation -; -; by Toshiyasu Morita -; -; Old code: -; -; 16b * 16b = 372 states (worst case) -; 32b * 32b = 724 states (worst case) -; -; New code: -; -; 16b * 16b = 48 states -; 16b * 32b = 72 states -; 32b * 32b = 92 states -; - - .global __mulsi3 -__mulsi3: - mov.w r1,r2 ; ( 2 states) b * d - mulxu r0,er2 ; (22 states) - - mov.w e0,r3 ; ( 2 states) a * d - beq L_skip1 ; ( 4 states) - mulxu r1,er3 ; (22 states) - add.w r3,e2 ; ( 2 states) - -L_skip1: - mov.w e1,r3 ; ( 2 states) c * b - beq L_skip2 ; ( 4 states) - mulxu r0,er3 ; (22 states) - add.w r3,e2 ; ( 2 states) - -L_skip2: - mov.l er2,er0 ; ( 2 states) - rts ; (10 states) - - .end diff --git a/arch/h8300/lib/ucmpdi2.c b/arch/h8300/lib/ucmpdi2.c deleted file mode 100644 index 9f646885f3d7..000000000000 --- a/arch/h8300/lib/ucmpdi2.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "libgcc.h" - -word_type __ucmpdi2(DWtype a, DWtype b) -{ - const DWunion au = {.ll = a}; - const DWunion bu = {.ll = b}; - - if ((UWtype) au.s.high < (UWtype) bu.s.high) - return 0; - else if ((UWtype) au.s.high > (UWtype) bu.s.high) - return 2; - if ((UWtype) au.s.low < (UWtype) bu.s.low) - return 0; - else if ((UWtype) au.s.low > (UWtype) bu.s.low) - return 2; - return 1; -} diff --git a/arch/h8300/lib/udivsi3.S b/arch/h8300/lib/udivsi3.S deleted file mode 100644 index b810aba8e100..000000000000 --- a/arch/h8300/lib/udivsi3.S +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include "libgcc.h" - - ;; This function also computes the remainder and stores it in er3. - .global __udivsi3 -__udivsi3: - mov.w A1E,A1E ; denominator top word 0? - bne DenHighNonZero - - ; do it the easy way, see page 107 in manual - mov.w A0E,A2 - extu.l A2P - divxu.w A1,A2P - mov.w A2E,A0E - divxu.w A1,A0P - mov.w A0E,A3 - mov.w A2,A0E - extu.l A3P - rts - - ; er0 = er0 / er1 - ; er3 = er0 % er1 - ; trashes er1 er2 - ; expects er1 >= 2^16 -DenHighNonZero: - mov.l er0,er3 - mov.l er1,er2 -#ifdef CONFIG_CPU_H8300H -divmod_L21: - shlr.l er0 - shlr.l er2 ; make divisor < 2^16 - mov.w e2,e2 - bne divmod_L21 -#else - shlr.l #2,er2 ; make divisor < 2^16 - mov.w e2,e2 - beq divmod_L22A -divmod_L21: - shlr.l #2,er0 -divmod_L22: - shlr.l #2,er2 ; make divisor < 2^16 - mov.w e2,e2 - bne divmod_L21 -divmod_L22A: - rotxl.w r2 - bcs divmod_L23 - shlr.l er0 - bra divmod_L24 -divmod_L23: - rotxr.w r2 - shlr.l #2,er0 -divmod_L24: -#endif - ;; At this point, - ;; er0 contains shifted dividend - ;; er1 contains divisor - ;; er2 contains shifted divisor - ;; er3 contains dividend, later remainder - divxu.w r2,er0 ; r0 now contains the approximate quotient (AQ) - extu.l er0 - beq divmod_L25 - subs #1,er0 ; er0 = AQ - 1 - mov.w e1,r2 - mulxu.w r0,er2 ; er2 = upper (AQ - 1) * divisor - sub.w r2,e3 ; dividend - 65536 * er2 - mov.w r1,r2 - mulxu.w r0,er2 ; compute er3 = remainder (tentative) - sub.l er2,er3 ; er3 = dividend - (AQ - 1) * divisor -divmod_L25: - cmp.l er1,er3 ; is divisor < remainder? - blo divmod_L26 - adds #1,er0 - sub.l er1,er3 ; correct the remainder -divmod_L26: - rts - - .end diff --git a/arch/h8300/mm/Makefile b/arch/h8300/mm/Makefile deleted file mode 100644 index e85b5c91f5bc..000000000000 --- a/arch/h8300/mm/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux h8300-specific parts of the memory manager. -# - -obj-y := init.o fault.o memory.o diff --git a/arch/h8300/mm/fault.c b/arch/h8300/mm/fault.c deleted file mode 100644 index b465441f490d..000000000000 --- a/arch/h8300/mm/fault.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/mm/fault.c - * - * Copyright (C) 1998 D. Jeff Dionne , - * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) - * - * Based on: - * - * linux/arch/m68knommu/mm/fault.c - * linux/arch/m68k/mm/fault.c - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#include -#include -#include -#include - - -void die(const char *str, struct pt_regs *fp, unsigned long err); - -/* - * This routine handles page faults. It determines the problem, and - * then passes it off to one of the appropriate routines. - * - * error_code: - * bit 0 == 0 means no page found, 1 means protection fault - * bit 1 == 0 means read, 1 means write - * - * If this routine detects a bad access, it returns 1, otherwise it - * returns 0. - */ -asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, - unsigned long error_code) -{ -#ifdef DEBUG - pr_debug("regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n", - regs->sr, regs->pc, address, error_code); -#endif - -/* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - if ((unsigned long) address < PAGE_SIZE) - pr_alert("Unable to handle kernel NULL pointer dereference"); - else - pr_alert("Unable to handle kernel access"); - printk(" at virtual address %08lx\n", address); - if (!user_mode(regs)) - die("Oops", regs, error_code); - make_task_dead(SIGKILL); - - return 1; -} diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c deleted file mode 100644 index f7bf4693e3b2..000000000000 --- a/arch/h8300/mm/init.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/mm/init.c - * - * Copyright (C) 1998 D. Jeff Dionne , - * Kenneth Albanowski , - * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) - * - * Based on: - * - * linux/arch/m68knommu/mm/init.c - * linux/arch/m68k/mm/init.c - * - * Copyright (C) 1995 Hamish Macdonald - * - * JAN/1999 -- hacked to support ColdFire (gerg@snapgear.com) - * DEC/2000 -- linux 2.4 support - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * ZERO_PAGE is a special page that is used for zero-initialized - * data and COW. - */ -unsigned long empty_zero_page; - -/* - * paging_init() continues the virtual memory environment setup which - * was begun by the code in arch/head.S. - * The parameters are pointers to where to stick the starting and ending - * addresses of available kernel virtual memory. - */ -void __init paging_init(void) -{ - /* - * Make sure start_mem is page aligned, otherwise bootmem and - * page_alloc get different views og the world. - */ - unsigned long start_mem = PAGE_ALIGN(memory_start); - unsigned long end_mem = memory_end & PAGE_MASK; - - pr_debug("start_mem is %#lx\nvirtual_end is %#lx\n", - start_mem, end_mem); - - /* - * Initialize the bad page table and bad page to point - * to a couple of allocated pages. - */ - empty_zero_page = (unsigned long)memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!empty_zero_page) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); - - /* - * Set up SFC/DFC registers (user data space). - */ - set_fs(USER_DS); - - pr_debug("before free_area_init\n"); - - pr_debug("free_area_init -> start_mem is %#lx\nvirtual_end is %#lx\n", - start_mem, end_mem); - - { - unsigned long max_zone_pfn[MAX_NR_ZONES] = {0, }; - - max_zone_pfn[ZONE_NORMAL] = end_mem >> PAGE_SHIFT; - free_area_init(max_zone_pfn); - } -} - -void __init mem_init(void) -{ - pr_devel("Mem_init: start=%lx, end=%lx\n", memory_start, memory_end); - - high_memory = (void *) (memory_end & PAGE_MASK); - max_mapnr = MAP_NR(high_memory); - - /* this will put all low memory onto the freelists */ - memblock_free_all(); -} diff --git a/arch/h8300/mm/memory.c b/arch/h8300/mm/memory.c deleted file mode 100644 index 4a60e2b5eb96..000000000000 --- a/arch/h8300/mm/memory.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/mm/memory.c - * - * Copyright (C) 2002 Yoshinori Sato , - * - * Based on: - * - * linux/arch/m68knommu/mm/memory.c - * - * Copyright (C) 1998 Kenneth Albanowski , - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * - * Based on: - * - * linux/arch/m68k/mm/memory.c - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -void cache_clear(unsigned long paddr, int len) -{ -} - - -void cache_push(unsigned long paddr, int len) -{ -} - -void cache_push_v(unsigned long vaddr, int len) -{ -} - -/* - * Map some physical address range into the kernel address space. - */ - -unsigned long kernel_map(unsigned long paddr, unsigned long size, - int nocacheflag, unsigned long *memavailp) -{ - return paddr; -} diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..955fbce86843 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -81,7 +81,6 @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ -obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/h8300/Makefile b/drivers/clk/h8300/Makefile deleted file mode 100644 index 8078a0b79000..000000000000 --- a/drivers/clk/h8300/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += clk-div.o -obj-$(CONFIG_H8S2678) += clk-h8s2678.o diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c deleted file mode 100644 index 376be03bb546..000000000000 --- a/drivers/clk/h8300/clk-div.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8/300 divide clock driver - * - * Copyright 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include - -static DEFINE_SPINLOCK(clklock); - -static void __init h8300_div_clk_setup(struct device_node *node) -{ - unsigned int num_parents; - struct clk_hw *hw; - const char *clk_name = node->name; - const char *parent_name; - void __iomem *divcr = NULL; - int width; - int offset; - - num_parents = of_clk_get_parent_count(node); - if (!num_parents) { - pr_err("%s: no parent found\n", clk_name); - return; - } - - divcr = of_iomap(node, 0); - if (divcr == NULL) { - pr_err("%s: failed to map divide register\n", clk_name); - goto error; - } - offset = (unsigned long)divcr & 3; - offset = (3 - offset) * 8; - divcr = (void __iomem *)((unsigned long)divcr & ~3); - - parent_name = of_clk_get_parent_name(node, 0); - of_property_read_u32(node, "renesas,width", &width); - hw = clk_hw_register_divider(NULL, clk_name, parent_name, - CLK_SET_RATE_GATE, divcr, offset, width, - CLK_DIVIDER_POWER_OF_TWO, &clklock); - if (!IS_ERR(hw)) { - of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); - return; - } - pr_err("%s: failed to register %s div clock (%ld)\n", - __func__, clk_name, PTR_ERR(hw)); -error: - if (divcr) - iounmap(divcr); -} - -CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup); diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c deleted file mode 100644 index 67c495b67c18..000000000000 --- a/drivers/clk/h8300/clk-h8s2678.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8S2678 clock driver - * - * Copyright 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include -#include - -static DEFINE_SPINLOCK(clklock); - -#define MAX_FREQ 33333333 -#define MIN_FREQ 8000000 - -struct pll_clock { - struct clk_hw hw; - void __iomem *sckcr; - void __iomem *pllcr; -}; - -#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw) - -static unsigned long pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct pll_clock *pll_clock = to_pll_clock(hw); - int mul = 1 << (readb(pll_clock->pllcr) & 3); - - return parent_rate * mul; -} - -static long pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - int i, m = -1; - long offset[3]; - - if (rate > MAX_FREQ) - rate = MAX_FREQ; - if (rate < MIN_FREQ) - rate = MIN_FREQ; - - for (i = 0; i < 3; i++) - offset[i] = abs(rate - (*prate * (1 << i))); - for (i = 0; i < 3; i++) - if (m < 0) - m = i; - else - m = (offset[i] < offset[m])?i:m; - - return *prate * (1 << m); -} - -static int pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - int pll; - unsigned char val; - unsigned long flags; - struct pll_clock *pll_clock = to_pll_clock(hw); - - pll = ((rate / parent_rate) / 2) & 0x03; - spin_lock_irqsave(&clklock, flags); - val = readb(pll_clock->sckcr); - val |= 0x08; - writeb(val, pll_clock->sckcr); - val = readb(pll_clock->pllcr); - val &= ~0x03; - val |= pll; - writeb(val, pll_clock->pllcr); - spin_unlock_irqrestore(&clklock, flags); - return 0; -} - -static const struct clk_ops pll_ops = { - .recalc_rate = pll_recalc_rate, - .round_rate = pll_round_rate, - .set_rate = pll_set_rate, -}; - -static void __init h8s2678_pll_clk_setup(struct device_node *node) -{ - unsigned int num_parents; - const char *clk_name = node->name; - const char *parent_name; - struct pll_clock *pll_clock; - struct clk_init_data init; - int ret; - - num_parents = of_clk_get_parent_count(node); - if (!num_parents) { - pr_err("%s: no parent found\n", clk_name); - return; - } - - - pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL); - if (!pll_clock) - return; - - pll_clock->sckcr = of_iomap(node, 0); - if (pll_clock->sckcr == NULL) { - pr_err("%s: failed to map divide register\n", clk_name); - goto free_clock; - } - - pll_clock->pllcr = of_iomap(node, 1); - if (pll_clock->pllcr == NULL) { - pr_err("%s: failed to map multiply register\n", clk_name); - goto unmap_sckcr; - } - - parent_name = of_clk_get_parent_name(node, 0); - init.name = clk_name; - init.ops = &pll_ops; - init.flags = 0; - init.parent_names = &parent_name; - init.num_parents = 1; - pll_clock->hw.init = &init; - - ret = clk_hw_register(NULL, &pll_clock->hw); - if (ret) { - pr_err("%s: failed to register %s div clock (%d)\n", - __func__, clk_name, ret); - goto unmap_pllcr; - } - - of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw); - return; - -unmap_pllcr: - iounmap(pll_clock->pllcr); -unmap_sckcr: - iounmap(pll_clock->sckcr); -free_clock: - kfree(pll_clock); -} - -CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock", - h8s2678_pll_clk_setup); diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cfb8ea0df3b1..4aa0883b3534 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -567,26 +567,6 @@ config CLKSRC_PXA This enables OST0 support available on PXA and SA-11x0 platforms. -config H8300_TMR8 - bool "Clockevent timer for the H8300 platform" if COMPILE_TEST - depends on HAS_IOMEM - help - This enables the 8 bits timer for the H8300 platform. - -config H8300_TMR16 - bool "Clockevent timer for the H83069 platform" if COMPILE_TEST - depends on HAS_IOMEM - help - This enables the 16 bits timer for the H8300 platform with the - H83069 CPU. - -config H8300_TPU - bool "Clocksource for the H8300 platform" if COMPILE_TEST - depends on HAS_IOMEM - help - This enables the clocksource for the H8300 platform with the - H8S2678 CPU. - config CLKSRC_IMX_GPT bool "Clocksource using i.MX GPT" if COMPILE_TEST depends on (ARM || ARM64) && HAVE_CLK diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index fa5f624eadb6..8e81eadfbeeb 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -73,9 +73,6 @@ obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_TIMER_IMX_SYS_CTR) += timer-imx-sysctr.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o -obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o -obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o -obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_INGENIC_OST) += ingenic-ost.o obj-$(CONFIG_INGENIC_SYSOST) += ingenic-sysost.o obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o diff --git a/drivers/clocksource/h8300_timer16.c b/drivers/clocksource/h8300_timer16.c deleted file mode 100644 index 86ca91451b2e..000000000000 --- a/drivers/clocksource/h8300_timer16.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8/300 16bit Timer driver - * - * Copyright 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define TSTR 0 -#define TISRC 6 - -#define TCR 0 -#define TCNT 2 - -#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a)) -#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a)) - -struct timer16_priv { - struct clocksource cs; - unsigned long total_cycles; - void __iomem *mapbase; - void __iomem *mapcommon; - unsigned short cs_enabled; - unsigned char enb; - unsigned char ovf; - unsigned char ovie; -}; - -static unsigned long timer16_get_counter(struct timer16_priv *p) -{ - unsigned short v1, v2, v3; - unsigned char o1, o2; - - o1 = ioread8(p->mapcommon + TISRC) & p->ovf; - - /* Make sure the timer value is stable. Stolen from acpi_pm.c */ - do { - o2 = o1; - v1 = ioread16be(p->mapbase + TCNT); - v2 = ioread16be(p->mapbase + TCNT); - v3 = ioread16be(p->mapbase + TCNT); - o1 = ioread8(p->mapcommon + TISRC) & p->ovf; - } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) - || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); - - if (likely(!o1)) - return v2; - else - return v2 + 0x10000; -} - - -static irqreturn_t timer16_interrupt(int irq, void *dev_id) -{ - struct timer16_priv *p = (struct timer16_priv *)dev_id; - - bclr(p->ovf, p->mapcommon + TISRC); - p->total_cycles += 0x10000; - - return IRQ_HANDLED; -} - -static inline struct timer16_priv *cs_to_priv(struct clocksource *cs) -{ - return container_of(cs, struct timer16_priv, cs); -} - -static u64 timer16_clocksource_read(struct clocksource *cs) -{ - struct timer16_priv *p = cs_to_priv(cs); - unsigned long raw, value; - - value = p->total_cycles; - raw = timer16_get_counter(p); - - return value + raw; -} - -static int timer16_enable(struct clocksource *cs) -{ - struct timer16_priv *p = cs_to_priv(cs); - - WARN_ON(p->cs_enabled); - - p->total_cycles = 0; - iowrite16be(0x0000, p->mapbase + TCNT); - iowrite8(0x83, p->mapbase + TCR); - bset(p->ovie, p->mapcommon + TISRC); - bset(p->enb, p->mapcommon + TSTR); - - p->cs_enabled = true; - return 0; -} - -static void timer16_disable(struct clocksource *cs) -{ - struct timer16_priv *p = cs_to_priv(cs); - - WARN_ON(!p->cs_enabled); - - bclr(p->ovie, p->mapcommon + TISRC); - bclr(p->enb, p->mapcommon + TSTR); - - p->cs_enabled = false; -} - -static struct timer16_priv timer16_priv = { - .cs = { - .name = "h8300_16timer", - .rating = 200, - .read = timer16_clocksource_read, - .enable = timer16_enable, - .disable = timer16_disable, - .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - }, -}; - -#define REG_CH 0 -#define REG_COMM 1 - -static int __init h8300_16timer_init(struct device_node *node) -{ - void __iomem *base[2]; - int ret, irq; - unsigned int ch; - struct clk *clk; - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("failed to get clock for clocksource\n"); - return PTR_ERR(clk); - } - - ret = -ENXIO; - base[REG_CH] = of_iomap(node, 0); - if (!base[REG_CH]) { - pr_err("failed to map registers for clocksource\n"); - goto free_clk; - } - - base[REG_COMM] = of_iomap(node, 1); - if (!base[REG_COMM]) { - pr_err("failed to map registers for clocksource\n"); - goto unmap_ch; - } - - ret = -EINVAL; - irq = irq_of_parse_and_map(node, 0); - if (!irq) { - pr_err("failed to get irq for clockevent\n"); - goto unmap_comm; - } - - of_property_read_u32(node, "renesas,channel", &ch); - - timer16_priv.mapbase = base[REG_CH]; - timer16_priv.mapcommon = base[REG_COMM]; - timer16_priv.enb = ch; - timer16_priv.ovf = ch; - timer16_priv.ovie = 4 + ch; - - ret = request_irq(irq, timer16_interrupt, - IRQF_TIMER, timer16_priv.cs.name, &timer16_priv); - if (ret < 0) { - pr_err("failed to request irq %d of clocksource\n", irq); - goto unmap_comm; - } - - clocksource_register_hz(&timer16_priv.cs, - clk_get_rate(clk) / 8); - return 0; - -unmap_comm: - iounmap(base[REG_COMM]); -unmap_ch: - iounmap(base[REG_CH]); -free_clk: - clk_put(clk); - return ret; -} - -TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer", - h8300_16timer_init); diff --git a/drivers/clocksource/h8300_timer8.c b/drivers/clocksource/h8300_timer8.c deleted file mode 100644 index 47114c2a7cb5..000000000000 --- a/drivers/clocksource/h8300_timer8.c +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/h8300/kernel/cpu/timer/timer8.c - * - * Yoshinori Sato - * - * 8bit Timer driver - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define _8TCR 0 -#define _8TCSR 2 -#define TCORA 4 -#define TCORB 6 -#define _8TCNT 8 - -#define CMIEA 6 -#define CMFA 6 - -#define FLAG_STARTED (1 << 3) - -#define SCALE 64 - -#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a)) -#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a)) - -struct timer8_priv { - struct clock_event_device ced; - void __iomem *mapbase; - unsigned long flags; - unsigned int rate; -}; - -static irqreturn_t timer8_interrupt(int irq, void *dev_id) -{ - struct timer8_priv *p = dev_id; - - if (clockevent_state_oneshot(&p->ced)) - iowrite16be(0x0000, p->mapbase + _8TCR); - - p->ced.event_handler(&p->ced); - - bclr(CMFA, p->mapbase + _8TCSR); - - return IRQ_HANDLED; -} - -static void timer8_set_next(struct timer8_priv *p, unsigned long delta) -{ - if (delta >= 0x10000) - pr_warn("delta out of range\n"); - bclr(CMIEA, p->mapbase + _8TCR); - iowrite16be(delta, p->mapbase + TCORA); - iowrite16be(0x0000, p->mapbase + _8TCNT); - bclr(CMFA, p->mapbase + _8TCSR); - bset(CMIEA, p->mapbase + _8TCR); -} - -static int timer8_enable(struct timer8_priv *p) -{ - iowrite16be(0xffff, p->mapbase + TCORA); - iowrite16be(0x0000, p->mapbase + _8TCNT); - iowrite16be(0x0c02, p->mapbase + _8TCR); - - return 0; -} - -static int timer8_start(struct timer8_priv *p) -{ - int ret; - - if ((p->flags & FLAG_STARTED)) - return 0; - - ret = timer8_enable(p); - if (!ret) - p->flags |= FLAG_STARTED; - - return ret; -} - -static void timer8_stop(struct timer8_priv *p) -{ - iowrite16be(0x0000, p->mapbase + _8TCR); -} - -static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced) -{ - return container_of(ced, struct timer8_priv, ced); -} - -static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta) -{ - timer8_start(p); - timer8_set_next(p, delta); -} - -static int timer8_clock_event_shutdown(struct clock_event_device *ced) -{ - timer8_stop(ced_to_priv(ced)); - return 0; -} - -static int timer8_clock_event_periodic(struct clock_event_device *ced) -{ - struct timer8_priv *p = ced_to_priv(ced); - - pr_info("%s: used for periodic clock events\n", ced->name); - timer8_stop(p); - timer8_clock_event_start(p, (p->rate + HZ/2) / HZ); - - return 0; -} - -static int timer8_clock_event_oneshot(struct clock_event_device *ced) -{ - struct timer8_priv *p = ced_to_priv(ced); - - pr_info("%s: used for oneshot clock events\n", ced->name); - timer8_stop(p); - timer8_clock_event_start(p, 0x10000); - - return 0; -} - -static int timer8_clock_event_next(unsigned long delta, - struct clock_event_device *ced) -{ - struct timer8_priv *p = ced_to_priv(ced); - - BUG_ON(!clockevent_state_oneshot(ced)); - timer8_set_next(p, delta - 1); - - return 0; -} - -static struct timer8_priv timer8_priv = { - .ced = { - .name = "h8300_8timer", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = timer8_clock_event_next, - .set_state_shutdown = timer8_clock_event_shutdown, - .set_state_periodic = timer8_clock_event_periodic, - .set_state_oneshot = timer8_clock_event_oneshot, - }, -}; - -static int __init h8300_8timer_init(struct device_node *node) -{ - void __iomem *base; - int irq, ret; - struct clk *clk; - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("failed to get clock for clockevent\n"); - return PTR_ERR(clk); - } - - ret = -ENXIO; - base = of_iomap(node, 0); - if (!base) { - pr_err("failed to map registers for clockevent\n"); - goto free_clk; - } - - ret = -EINVAL; - irq = irq_of_parse_and_map(node, 0); - if (!irq) { - pr_err("failed to get irq for clockevent\n"); - goto unmap_reg; - } - - timer8_priv.mapbase = base; - - timer8_priv.rate = clk_get_rate(clk) / SCALE; - if (!timer8_priv.rate) { - pr_err("Failed to get rate for the clocksource\n"); - goto unmap_reg; - } - - if (request_irq(irq, timer8_interrupt, IRQF_TIMER, - timer8_priv.ced.name, &timer8_priv) < 0) { - pr_err("failed to request irq %d for clockevent\n", irq); - goto unmap_reg; - } - - clockevents_config_and_register(&timer8_priv.ced, - timer8_priv.rate, 1, 0x0000ffff); - - return 0; -unmap_reg: - iounmap(base); -free_clk: - clk_put(clk); - return ret; -} - -TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init); diff --git a/drivers/clocksource/h8300_tpu.c b/drivers/clocksource/h8300_tpu.c deleted file mode 100644 index 17d4ab0f6ad1..000000000000 --- a/drivers/clocksource/h8300_tpu.c +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8S TPU Driver - * - * Copyright 2015 Yoshinori Sato - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TCR 0x0 -#define TSR 0x5 -#define TCNT 0x6 - -#define TCFV 0x10 - -struct tpu_priv { - struct clocksource cs; - void __iomem *mapbase1; - void __iomem *mapbase2; - raw_spinlock_t lock; - unsigned int cs_enabled; -}; - -static inline unsigned long read_tcnt32(struct tpu_priv *p) -{ - unsigned long tcnt; - - tcnt = ioread16be(p->mapbase1 + TCNT) << 16; - tcnt |= ioread16be(p->mapbase2 + TCNT); - return tcnt; -} - -static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val) -{ - unsigned long v1, v2, v3; - int o1, o2; - - o1 = ioread8(p->mapbase1 + TSR) & TCFV; - - /* Make sure the timer value is stable. Stolen from acpi_pm.c */ - do { - o2 = o1; - v1 = read_tcnt32(p); - v2 = read_tcnt32(p); - v3 = read_tcnt32(p); - o1 = ioread8(p->mapbase1 + TSR) & TCFV; - } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) - || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); - - *val = v2; - return o1; -} - -static inline struct tpu_priv *cs_to_priv(struct clocksource *cs) -{ - return container_of(cs, struct tpu_priv, cs); -} - -static u64 tpu_clocksource_read(struct clocksource *cs) -{ - struct tpu_priv *p = cs_to_priv(cs); - unsigned long flags; - unsigned long long value; - - raw_spin_lock_irqsave(&p->lock, flags); - if (tpu_get_counter(p, &value)) - value += 0x100000000; - raw_spin_unlock_irqrestore(&p->lock, flags); - - return value; -} - -static int tpu_clocksource_enable(struct clocksource *cs) -{ - struct tpu_priv *p = cs_to_priv(cs); - - WARN_ON(p->cs_enabled); - - iowrite16be(0, p->mapbase1 + TCNT); - iowrite16be(0, p->mapbase2 + TCNT); - iowrite8(0x0f, p->mapbase1 + TCR); - iowrite8(0x03, p->mapbase2 + TCR); - - p->cs_enabled = true; - return 0; -} - -static void tpu_clocksource_disable(struct clocksource *cs) -{ - struct tpu_priv *p = cs_to_priv(cs); - - WARN_ON(!p->cs_enabled); - - iowrite8(0, p->mapbase1 + TCR); - iowrite8(0, p->mapbase2 + TCR); - p->cs_enabled = false; -} - -static struct tpu_priv tpu_priv = { - .cs = { - .name = "H8S_TPU", - .rating = 200, - .read = tpu_clocksource_read, - .enable = tpu_clocksource_enable, - .disable = tpu_clocksource_disable, - .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - }, -}; - -#define CH_L 0 -#define CH_H 1 - -static int __init h8300_tpu_init(struct device_node *node) -{ - void __iomem *base[2]; - struct clk *clk; - int ret = -ENXIO; - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("failed to get clock for clocksource\n"); - return PTR_ERR(clk); - } - - base[CH_L] = of_iomap(node, CH_L); - if (!base[CH_L]) { - pr_err("failed to map registers for clocksource\n"); - goto free_clk; - } - base[CH_H] = of_iomap(node, CH_H); - if (!base[CH_H]) { - pr_err("failed to map registers for clocksource\n"); - goto unmap_L; - } - - tpu_priv.mapbase1 = base[CH_L]; - tpu_priv.mapbase2 = base[CH_H]; - - return clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64); - -unmap_L: - iounmap(base[CH_H]); -free_clk: - clk_put(clk); - return ret; -} - -TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init); diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7038957f4a77..95f5d14557f3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -330,17 +330,6 @@ config INGENIC_TCU_IRQ If unsure, say N. -config RENESAS_H8300H_INTC - bool - select IRQ_DOMAIN - -config RENESAS_H8S_INTC - bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST - select IRQ_DOMAIN - help - Enable support for the Renesas H8/300 Interrupt Controller, as found - on Renesas H8S SoCs. - config IMX_GPCV2 bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index c1f611cbfbf8..e555dba371bf 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -70,8 +70,6 @@ obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o irq-mtk-cirq.o obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o -obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o -obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_INGENIC_TCU_IRQ) += irq-ingenic-tcu.o diff --git a/drivers/irqchip/irq-renesas-h8300h.c b/drivers/irqchip/irq-renesas-h8300h.c deleted file mode 100644 index 1054d74b7edd..000000000000 --- a/drivers/irqchip/irq-renesas-h8300h.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8/300H interrupt controller driver - * - * Copyright 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include -#include - -static const char ipr_bit[] = { - 7, 6, 5, 5, - 4, 4, 4, 4, 3, 3, 3, 3, - 2, 2, 2, 2, 1, 1, 1, 1, - 0, 0, 0, 0, 15, 15, 15, 15, - 14, 14, 14, 14, 13, 13, 13, 13, - -1, -1, -1, -1, 11, 11, 11, 11, - 10, 10, 10, 10, 9, 9, 9, 9, -}; - -static void __iomem *intc_baseaddr; - -#define IPR (intc_baseaddr + 6) - -static void h8300h_disable_irq(struct irq_data *data) -{ - int bit; - int irq = data->irq - 12; - - bit = ipr_bit[irq]; - if (bit >= 0) { - if (bit < 8) - ctrl_bclr(bit & 7, IPR); - else - ctrl_bclr(bit & 7, (IPR+1)); - } -} - -static void h8300h_enable_irq(struct irq_data *data) -{ - int bit; - int irq = data->irq - 12; - - bit = ipr_bit[irq]; - if (bit >= 0) { - if (bit < 8) - ctrl_bset(bit & 7, IPR); - else - ctrl_bset(bit & 7, (IPR+1)); - } -} - -struct irq_chip h8300h_irq_chip = { - .name = "H8/300H-INTC", - .irq_enable = h8300h_enable_irq, - .irq_disable = h8300h_disable_irq, -}; - -static int irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw_irq_num) -{ - irq_set_chip_and_handler(virq, &h8300h_irq_chip, handle_simple_irq); - - return 0; -} - -static const struct irq_domain_ops irq_ops = { - .map = irq_map, - .xlate = irq_domain_xlate_onecell, -}; - -static int __init h8300h_intc_of_init(struct device_node *intc, - struct device_node *parent) -{ - struct irq_domain *domain; - - intc_baseaddr = of_iomap(intc, 0); - BUG_ON(!intc_baseaddr); - - /* All interrupt priority low */ - writeb(0x00, IPR + 0); - writeb(0x00, IPR + 1); - - domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); - BUG_ON(!domain); - irq_set_default_host(domain); - return 0; -} - -IRQCHIP_DECLARE(h8300h_intc, "renesas,h8300h-intc", h8300h_intc_of_init); diff --git a/drivers/irqchip/irq-renesas-h8s.c b/drivers/irqchip/irq-renesas-h8s.c deleted file mode 100644 index 4e2461bae944..000000000000 --- a/drivers/irqchip/irq-renesas-h8s.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * H8S interrupt controller driver - * - * Copyright 2015 Yoshinori Sato - */ - -#include -#include -#include -#include -#include - -static void *intc_baseaddr; -#define IPRA (intc_baseaddr) - -static const unsigned char ipr_table[] = { - 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */ - 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */ - 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */ - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */ - 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */ - 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */ - 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */ - 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */ - 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */ - 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */ - 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */ - 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */ - 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */ - 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */ -}; - -static void h8s_disable_irq(struct irq_data *data) -{ - int pos; - void __iomem *addr; - unsigned short pri; - int irq = data->irq; - - addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3); - pos = (ipr_table[irq - 16] & 0x0f) * 4; - pri = ~(0x000f << pos); - pri &= readw(addr); - writew(pri, addr); -} - -static void h8s_enable_irq(struct irq_data *data) -{ - int pos; - void __iomem *addr; - unsigned short pri; - int irq = data->irq; - - addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3); - pos = (ipr_table[irq - 16] & 0x0f) * 4; - pri = ~(0x000f << pos); - pri &= readw(addr); - pri |= 1 << pos; - writew(pri, addr); -} - -struct irq_chip h8s_irq_chip = { - .name = "H8S-INTC", - .irq_enable = h8s_enable_irq, - .irq_disable = h8s_disable_irq, -}; - -static __init int irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw_irq_num) -{ - irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq); - - return 0; -} - -static const struct irq_domain_ops irq_ops = { - .map = irq_map, - .xlate = irq_domain_xlate_onecell, -}; - -static int __init h8s_intc_of_init(struct device_node *intc, - struct device_node *parent) -{ - struct irq_domain *domain; - int n; - - intc_baseaddr = of_iomap(intc, 0); - BUG_ON(!intc_baseaddr); - - /* All interrupt priority is 0 (disable) */ - /* IPRA to IPRK */ - for (n = 0; n <= 'k' - 'a'; n++) - writew(0x0000, IPRA + (n * 2)); - - domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); - BUG_ON(!domain); - irq_set_default_host(domain); - return 0; -} - -IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init); diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig index 72e42a868346..2524c907f386 100644 --- a/drivers/net/ethernet/smsc/Kconfig +++ b/drivers/net/ethernet/smsc/Kconfig @@ -8,7 +8,7 @@ config NET_VENDOR_SMSC default y depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \ ISA || MAC || MIPS || NIOS2 || PCI || \ - PCMCIA || SUPERH || XTENSA || H8300 || COMPILE_TEST + PCMCIA || SUPERH || XTENSA || COMPILE_TEST help If you have a network (Ethernet) card belonging to this class, say Y. @@ -40,7 +40,7 @@ config SMC91X select MII depends on !OF || GPIOLIB depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \ - MIPS || NIOS2 || SUPERH || XTENSA || H8300 || COMPILE_TEST + MIPS || NIOS2 || SUPERH || XTENSA || COMPILE_TEST help This is a driver for SMC's 91x series of Ethernet chipsets, including the SMC91C94 and the SMC91C111. Say Y if you want it diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index 387539a8094b..c521ea8f94f2 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -182,17 +182,6 @@ static inline void mcf_outsw(void *a, unsigned char *p, int l) #define SMC_IRQ_FLAGS 0 -#elif defined(CONFIG_H8300) -#define SMC_CAN_USE_8BIT 1 -#define SMC_CAN_USE_16BIT 0 -#define SMC_CAN_USE_32BIT 0 -#define SMC_NOWAIT 0 - -#define SMC_inb(a, r) ioread8((a) + (r)) -#define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) -#define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l) -#define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l) - #else /* diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0e5ccb25bdb1..3eaf8fbd76f9 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -653,7 +653,7 @@ config SERIAL_IP22_ZILOG_CONSOLE config SERIAL_SH_SCI tristate "SuperH SCI(F) serial port support" - depends on SUPERH || ARCH_RENESAS || H8300 || COMPILE_TEST + depends on SUPERH || ARCH_RENESAS || COMPILE_TEST select SERIAL_CORE select SERIAL_MCTRL_GPIO if GPIOLIB @@ -662,7 +662,6 @@ config SERIAL_SH_SCI_NR_UARTS range 1 64 if 64BIT range 1 32 if !64BIT depends on SERIAL_SH_SCI - default "3" if H8300 default "10" if SUPERH default "18" if ARCH_RENESAS default "2" @@ -678,7 +677,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS || H8300 + default ARCH_RENESAS config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERT diff --git a/init/Kconfig b/init/Kconfig index e9119bf54b1f..9a11d3755811 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -711,8 +711,7 @@ config IKHEADERS config LOG_BUF_SHIFT int "Kernel log buffer size (16 => 64KB, 17 => 128KB)" - range 12 25 if !H8300 - range 12 19 if H8300 + range 12 25 default 17 depends on PRINTK help diff --git a/tools/arch/h8300/include/asm/bitsperlong.h b/tools/arch/h8300/include/asm/bitsperlong.h deleted file mode 100644 index fa1508337ffc..000000000000 --- a/tools/arch/h8300/include/asm/bitsperlong.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_H8300_BITS_PER_LONG -#define __ASM_H8300_BITS_PER_LONG - -#include - -#if !defined(__ASSEMBLY__) -/* h8300-unknown-linux required long */ -#define __kernel_size_t __kernel_size_t -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -#endif - -#endif /* __ASM_H8300_BITS_PER_LONG */ diff --git a/tools/arch/h8300/include/uapi/asm/mman.h b/tools/arch/h8300/include/uapi/asm/mman.h deleted file mode 100644 index be7bbe0528d1..000000000000 --- a/tools/arch/h8300/include/uapi/asm/mman.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef TOOLS_ARCH_H8300_UAPI_ASM_MMAN_FIX_H -#define TOOLS_ARCH_H8300_UAPI_ASM_MMAN_FIX_H -#include -/* MAP_32BIT is undefined on h8300, fix it for perf */ -#define MAP_32BIT 0 -#endif From 08ba32541b7a48078fe9cee5953097622f3774e9 Mon Sep 17 00:00:00 2001 From: Haowen Bai Date: Wed, 23 Mar 2022 12:02:03 +0800 Subject: [PATCH 0002/1268] fs: ext2: Fix duplicate included linux/dax.h Clean up the following includecheck warning: fs/ext2/inode.c: linux/dax.h is included more than once. No functional change. Signed-off-by: Haowen Bai Reviewed-by: Ritesh Harjani Signed-off-by: Jan Kara Link: https://lore.kernel.org/r/1648008123-32485-1-git-send-email-baihaowen@meizu.com --- fs/ext2/inode.c | 1 - 1 file changed, 1 deletion(-) diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c index 52377a0ee735..d6875d733f96 100644 --- a/fs/ext2/inode.c +++ b/fs/ext2/inode.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "ext2.h" #include "acl.h" #include "xattr.h" From 7e5a7e39d767b60d8631792bd3d7820a6f4a43f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:52:10 +0200 Subject: [PATCH 0003/1268] ARM: dts: rockchip: correct interrupt flags on rk3188 boards GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags without affecting the code: ACTIVE_HIGH => IRQ_TYPE_NONE Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200917185211.5483-1-krzk@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 85d3fce0142f..35b7a5798eee 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include #include "rk3188.dtsi" / { @@ -485,7 +486,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio3>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; From 146c9a346fdd0506228cace62cf324e4c1e3705a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 31 Mar 2022 14:56:44 +0200 Subject: [PATCH 0004/1268] ARM: dts: rockchip: use generic node name for dma rk3036/rk322x The node names should be generic, so fix this for the rk3036 and rk322x dma node and rename it to "dma-controller". Signed-off-by: Johan Jonker Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220331125644.6841-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 2 +- arch/arm/boot/dts/rk322x.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ba2b8891bbb7..477a8d0030c2 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -556,7 +556,7 @@ status = "disabled"; }; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; interrupts = , diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5868eb512f69..6513ffcaac92 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -501,7 +501,7 @@ <75000000>; }; - pdma: pdma@110f0000 { + pdma: dma-controller@110f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x110f0000 0x4000>; interrupts = , From 2bda08dfc501967a7a7bd6f77f04afef14dc7271 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:07 +0300 Subject: [PATCH 0005/1268] arm64: meson: add dts bluetooth node for JetHub H1 Add bluetooth node for RTL8822CS uart to JetHub H1 dts file. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-2-adeep@lexina.in --- .../boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 6eafb908695f..fcb304c5a40f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -213,6 +213,12 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; }; &uart_C { From cf94e26508ad411c2a618b00dfaae515affd0ca7 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:08 +0300 Subject: [PATCH 0006/1268] arm64: meson: dts: update serial alias in dts for JetHub D1 Change zigbee serial port alias to ttyAML2 for backward compatibility. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-3-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 561eec21b4de..9951217ef997 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -18,7 +18,7 @@ model = "JetHome JetHub J100"; aliases { serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + serial2 = &uart_AO_B; /* External UART (Wireless Module) */ ethernet0 = ðmac; }; From 81bbd2bd24a9ebac3871b293060df50445458c79 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:09 +0300 Subject: [PATCH 0007/1268] arm64: meson: update SDIO voltage in dts for JetHub D1 Fix the dts to match board's reference design: - update vddio_boot regulator to 3.3v (Wi-Fi SDIO module) - add vccq_1v8 regulator with 1.8v for eMMC SDIO In the first revision of JetHub D1 the vccq_1v8 regulator was 3.3v. All installed eMMC modules were tested to work in HS200 mode at 3.3v supply voltage. In the next revisions of the board eMMC will be powered with 1.8v according to the standard. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-4-adeep@lexina.in --- .../dts/amlogic/meson-axg-jethome-jethub-j100.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 9951217ef997..1ab3cedfbee5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -81,6 +81,15 @@ vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vccq_1v8: regulator-vccq_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vddao_3v3>; @@ -282,7 +291,7 @@ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; + vqmmc-supply = <&vccq_1v8>; }; /* UART Bluetooth */ From 87a87657249316616138c103c2bdb7525c34d987 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:10 +0300 Subject: [PATCH 0008/1268] arm64: meson: update WiFi SDIO in dts for JetHub D1 Fix the dts to match board's reference design: - update the maximum SDIO frequency to match 3.3v regulator (Wi-Fi SDIO module) Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-5-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 1ab3cedfbee5..8b0d586aa84e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -257,8 +257,7 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; + max-frequency = <50000000>; non-removable; disable-wp; From 4246d0bab2a8685e3d4aec2cb0ef8c526689ce96 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 15 Mar 2022 17:27:06 +0800 Subject: [PATCH 0009/1268] arm64: dts: rockchip: Move drive-impedance-ohm to emmc phy on rk3399 drive-impedance-ohm is introduced for emmc phy instead of pcie phy. Fixes: fb8b7460c995 ("arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy.") Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1647336426-154797-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 080457a68e3c..88f26d89eea1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1534,6 +1534,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk"; + drive-impedance-ohm = <50>; #phy-cells = <0>; status = "disabled"; }; @@ -1544,7 +1545,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; From 16c0f95d9ed14f033b5f1bd37e96d257b60c198c Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 11 Mar 2022 22:03:57 +0100 Subject: [PATCH 0010/1268] arm64: dts: rockchip: Add sata nodes to rk356x RK356x supports up to 3 sata controllers which were compatible with the existing snps,dwc-ahci binding. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220311210357.222830-7-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5b0f528d6818..3e07d9f6a2d1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,20 @@ / { compatible = "rockchip,rk3568"; + sata0: sata@fc000000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + pipe_phy_grf0: syscon@fdc70000 { compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; reg = <0x0 0xfdc70000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 7cdef800cb3c..264dd030e703 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -230,6 +230,34 @@ }; }; + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy2 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ From a070d3b857d4961e1202754f7a86a0f796f808cd Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 15 Mar 2022 22:08:10 +0000 Subject: [PATCH 0011/1268] arm64: dts: rockchip: Add some pins for NanoPi4 The NanoPi4 boards have the RK808's always-on 32KHz clock wired to the SoC, so have it claim the relevant pinctrl to actually enable the CLK32K_IN input. The RK808's SLEEP pin is also wired to the SoC's AP_PWROFF output, so we may as well claim that too. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/e870284a872567f163868b77267c01b77ed6f22a.1647381986.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 8c0ff6c96e03..248ad41a976b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -267,7 +267,7 @@ interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; + pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>; rockchip,system-power-controller; wakeup-source; From 6383f5a212a6b569ff15bc98ba8b3041a35db6ee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 11:04:10 +0800 Subject: [PATCH 0012/1268] arm64: dts: meson-s4: add pinctrl node Add pinctrl node for mesonn-s4 Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310030410.718-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index bf9ae1e1016b..e440efcf7a92 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { cpus { @@ -85,6 +86,22 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,meson-s4-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4000 { + reg = <0x0 0x4000 0x0 0x004c>, + <0x0 0x40c0 0x0 0x0220>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 82>; + }; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; From 393633936976fb8bd2c26ae76fa8d30822bb7fee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 17:26:45 +0800 Subject: [PATCH 0013/1268] arm64: dts: meson-s4: add gpio_intc node Add gpio interrupt controller node Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310092645.4303-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index e440efcf7a92..dcaf7d98a6f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -102,6 +102,16 @@ }; }; + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,meson-s4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; From 085f7a298a14ed2a088c8ba01d2feda2499cbc72 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Fri, 1 Apr 2022 19:03:06 +0800 Subject: [PATCH 0014/1268] arm64: dts: add support for S4 power domain controller Enable power domain controller for Meson s4 SoC Signed-off-by: Shunzhou Jiang Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220401110306.3364551-1-shunzhou.jiang@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index dcaf7d98a6f1..2e45a8ecd9a0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -61,6 +61,12 @@ #clock-cells = <0>; }; + pwrc: power-controller { + compatible = "amlogic,meson-s4-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; From d7445676e86900f8dc363825033ff62416c216e0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 1 Apr 2022 14:35:42 +0200 Subject: [PATCH 0015/1268] ARM: versatile: move integrator/realview/vexpress to versatile These are all fairly small platforms by now, and they are closely related. Just move them all into a single directory. Cc: Linus Walleij Cc: Liviu Dudau Cc: Lorenzo Pieralisi Tested-by: Sudeep Holla Acked-by: Sudeep Holla Signed-off-by: Arnd Bergmann --- MAINTAINERS | 3 - arch/arm/Kconfig | 6 - arch/arm/Makefile | 7 +- arch/arm/mach-integrator/Kconfig | 125 ------- arch/arm/mach-integrator/Makefile | 10 - arch/arm/mach-realview/Kconfig | 103 ------ arch/arm/mach-realview/Makefile | 8 - arch/arm/mach-versatile/Kconfig | 308 ++++++++++++++++++ arch/arm/mach-versatile/Makefile | 32 +- .../Makefile.boot | 0 .../{mach-vexpress => mach-versatile}/dcscb.c | 4 +- .../dcscb_setup.S | 2 - .../headsmp.S | 2 - .../hotplug.c | 2 +- .../cm.h => mach-versatile/integrator-cm.h} | 0 .../integrator-hardware.h} | 0 .../core.c => mach-versatile/integrator.c} | 8 +- .../common.h => mach-versatile/integrator.h} | 0 .../integrator_ap.c | 8 +- .../integrator_cp.c | 8 +- .../platsmp-realview.c} | 2 +- .../platsmp-vexpress.c} | 7 +- .../platsmp.c | 4 +- .../include/plat => mach-versatile}/platsmp.h | 2 - .../realview.c} | 0 .../{mach-vexpress => mach-versatile}/spc.c | 0 .../{mach-vexpress => mach-versatile}/spc.h | 0 .../tc2_pm.c | 2 - .../v2m-mps2.c | 0 .../{mach-vexpress => mach-versatile}/v2m.c | 2 +- .../{versatile_dt.c => versatile.c} | 0 .../core.h => mach-versatile/vexpress.h} | 0 arch/arm/mach-vexpress/Kconfig | 81 ----- arch/arm/mach-vexpress/Makefile | 19 -- arch/arm/plat-versatile/Makefile | 5 - 35 files changed, 357 insertions(+), 403 deletions(-) delete mode 100644 arch/arm/mach-integrator/Kconfig delete mode 100644 arch/arm/mach-integrator/Makefile delete mode 100644 arch/arm/mach-realview/Kconfig delete mode 100644 arch/arm/mach-realview/Makefile rename arch/arm/{mach-vexpress => mach-versatile}/Makefile.boot (100%) rename arch/arm/{mach-vexpress => mach-versatile}/dcscb.c (97%) rename arch/arm/{mach-vexpress => mach-versatile}/dcscb_setup.S (95%) rename arch/arm/{plat-versatile => mach-versatile}/headsmp.S (94%) rename arch/arm/{plat-versatile => mach-versatile}/hotplug.c (98%) rename arch/arm/{mach-integrator/cm.h => mach-versatile/integrator-cm.h} (100%) rename arch/arm/{mach-integrator/hardware.h => mach-versatile/integrator-hardware.h} (100%) rename arch/arm/{mach-integrator/core.c => mach-versatile/integrator.c} (95%) rename arch/arm/{mach-integrator/common.h => mach-versatile/integrator.h} (100%) rename arch/arm/{mach-integrator => mach-versatile}/integrator_ap.c (97%) rename arch/arm/{mach-integrator => mach-versatile}/integrator_cp.c (96%) rename arch/arm/{mach-realview/platsmp-dt.c => mach-versatile/platsmp-realview.c} (98%) rename arch/arm/{mach-vexpress/platsmp.c => mach-versatile/platsmp-vexpress.c} (96%) rename arch/arm/{plat-versatile => mach-versatile}/platsmp.c (97%) rename arch/arm/{plat-versatile/include/plat => mach-versatile}/platsmp.h (87%) rename arch/arm/{mach-realview/realview-dt.c => mach-versatile/realview.c} (100%) rename arch/arm/{mach-vexpress => mach-versatile}/spc.c (100%) rename arch/arm/{mach-vexpress => mach-versatile}/spc.h (100%) rename arch/arm/{mach-vexpress => mach-versatile}/tc2_pm.c (99%) rename arch/arm/{mach-vexpress => mach-versatile}/v2m-mps2.c (100%) rename arch/arm/{mach-vexpress => mach-versatile}/v2m.c (97%) rename arch/arm/mach-versatile/{versatile_dt.c => versatile.c} (100%) rename arch/arm/{mach-vexpress/core.h => mach-versatile/vexpress.h} (100%) delete mode 100644 arch/arm/mach-vexpress/Kconfig delete mode 100644 arch/arm/mach-vexpress/Makefile delete mode 100644 arch/arm/plat-versatile/Makefile diff --git a/MAINTAINERS b/MAINTAINERS index fd768d43e048..6a0363b0f106 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1525,10 +1525,7 @@ F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml F: arch/arm/boot/dts/arm-realview-* F: arch/arm/boot/dts/integrator* F: arch/arm/boot/dts/versatile* -F: arch/arm/mach-integrator/ -F: arch/arm/mach-realview/ F: arch/arm/mach-versatile/ -F: arch/arm/plat-versatile/ F: drivers/bus/arm-integrator-lm.c F: drivers/clk/versatile/ F: drivers/i2c/busses/i2c-versatile.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e8091e2d8a8..31f024e6e925 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -622,8 +622,6 @@ source "arch/arm/mach-hisi/Kconfig" source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-integrator/Kconfig" - source "arch/arm/mach-iop32x/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" @@ -675,8 +673,6 @@ source "arch/arm/mach-rda/Kconfig" source "arch/arm/mach-realtek/Kconfig" -source "arch/arm/mach-realview/Kconfig" - source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s3c/Kconfig" @@ -705,8 +701,6 @@ source "arch/arm/mach-ux500/Kconfig" source "arch/arm/mach-versatile/Kconfig" -source "arch/arm/mach-vexpress/Kconfig" - source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-zynq/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a2391b8de5a5..8740e3a63afb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi -machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone @@ -187,7 +186,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp -machine-$(CONFIG_ARCH_MPS2) += vexpress machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu @@ -207,7 +205,6 @@ machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom machine-$(CONFIG_ARCH_RDA) += rda machine-$(CONFIG_ARCH_REALTEK) += realtek -machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_PLAT_SAMSUNG) += s3c @@ -220,10 +217,9 @@ machine-$(CONFIG_ARCH_STM32) += stm32 machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += ux500 -machine-$(CONFIG_ARCH_VERSATILE) += versatile -machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_ZYNQ) += zynq +machine-$(CONFIG_PLAT_VERSATILE) += versatile machine-$(CONFIG_PLAT_SPEAR) += spear # Platform directory name. This list is sorted alphanumerically @@ -231,7 +227,6 @@ machine-$(CONFIG_PLAT_SPEAR) += spear plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa -plat-$(CONFIG_PLAT_VERSATILE) += versatile # The byte offset of the kernel image in RAM from the start of RAM. TEXT_OFFSET := $(textofs-y) diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig deleted file mode 100644 index d61ea616cf8e..000000000000 --- a/arch/arm/mach-integrator/Kconfig +++ /dev/null @@ -1,125 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_INTEGRATOR - bool "ARM Ltd. Integrator family" - depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 - select ARM_AMBA - select CMA - select DMA_CMA - select HAVE_TCM - select CLK_ICST - select MFD_SYSCON - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VERSATILE - select POWER_SUPPLY - select SOC_INTEGRATOR_CM - select VERSATILE_FPGA_IRQ - help - Support for ARM's Integrator platform. - -if ARCH_INTEGRATOR - -config ARCH_INTEGRATOR_AP - bool "Support Integrator/AP and Integrator/PP2 platforms" - select INTEGRATOR_AP_TIMER - select SERIAL_AMBA_PL010 if TTY - select SERIAL_AMBA_PL010_CONSOLE if TTY - select SOC_BUS - help - Include support for the ARM(R) Integrator/AP and - Integrator/PP2 platforms. - -config INTEGRATOR_IMPD1 - bool "Include support for Integrator/IM-PD1" - depends on ARCH_INTEGRATOR_AP - select ARM_VIC - select GPIO_PL061 - select GPIOLIB - select REGULATOR - select REGULATOR_FIXED_VOLTAGE - help - The IM-PD1 is an add-on logic module for the Integrator which - allows ARM(R) Ltd PrimeCells to be developed and evaluated. - The IM-PD1 can be found on the Integrator/PP2 platform. - -config INTEGRATOR_CM720T - bool "Integrator/CM720T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T - select CPU_ARM720T - -config INTEGRATOR_CM920T - bool "Integrator/CM920T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T - select CPU_ARM920T - -config INTEGRATOR_CM922T_XA10 - bool "Integrator/CM922T-XA10 core module" - depends on ARCH_MULTI_V4T - depends on ARCH_INTEGRATOR_AP - select CPU_ARM922T - -config INTEGRATOR_CM926EJS - bool "Integrator/CM926EJ-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM926T - -config INTEGRATOR_CM10200E_REV0 - bool "Integrator/CM10200E rev.0 core module" - depends on ARCH_INTEGRATOR_AP && n - depends on ARCH_MULTI_V5 - select CPU_ARM1020 - -config INTEGRATOR_CM10200E - bool "Integrator/CM10200E core module" - depends on ARCH_INTEGRATOR_AP && n - depends on ARCH_MULTI_V5 - select CPU_ARM1020E - -config INTEGRATOR_CM10220E - bool "Integrator/CM10220E core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM1022 - -config INTEGRATOR_CM1026EJS - bool "Integrator/CM1026EJ-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM1026 - -config INTEGRATOR_CM1136JFS - bool "Integrator/CM1136JF-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V6 - select CPU_V6 - -config ARCH_INTEGRATOR_CP - bool "Support Integrator/CP platform" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 - select ARM_TIMER_SP804 - select SERIAL_AMBA_PL011 if TTY - select SERIAL_AMBA_PL011_CONSOLE if TTY - select SOC_BUS - help - Include support for the ARM(R) Integrator CP platform. - -config INTEGRATOR_CT926 - bool "Integrator/CT926 (ARM926EJ-S) core tile" - depends on ARCH_INTEGRATOR_CP - depends on ARCH_MULTI_V5 - select CPU_ARM926T - -config INTEGRATOR_CTB36 - bool "Integrator/CTB36 (ARM1136JF-S) core tile" - depends on ARCH_INTEGRATOR_CP - depends on ARCH_MULTI_V6 - select CPU_V6 - -config ARCH_CINTEGRATOR - depends on ARCH_INTEGRATOR_CP - def_bool y - -endif diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile deleted file mode 100644 index 7857a55c90b0..000000000000 --- a/arch/arm/mach-integrator/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o -obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o -obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig deleted file mode 100644 index a4c36024b5e8..000000000000 --- a/arch/arm/mach-realview/Kconfig +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_REALVIEW - bool "ARM Ltd. RealView family" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 - select ARM_AMBA - select ARM_GIC - select ARM_TIMER_SP804 - select CLK_SP810 - select GPIO_PL061 if GPIOLIB - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_PATA_PLATFORM - select HAVE_TCM - select CLK_ICST - select MACH_REALVIEW_EB if ARCH_MULTI_V5 - select MFD_SYSCON - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VERSATILE - select POWER_SUPPLY - select SOC_REALVIEW - help - This enables support for ARM Ltd RealView boards. - -if ARCH_REALVIEW - -config MACH_REALVIEW_EB - bool "Support RealView(R) Emulation Baseboard" - select ARM_GIC - select CPU_ARM926T if ARCH_MULTI_V5 - help - Include support for the ARM(R) RealView(R) Emulation Baseboard - platform. On an ARMv5 kernel, this will include support for - the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least - one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore - core tile options should be enabled. - -config REALVIEW_EB_ARM1136 - bool "Support ARM1136J(F)-S Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - select CPU_V6 - help - Enable support for the ARM1136 tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_ARM1176 - bool "Support ARM1176JZ(F)-S Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - help - Enable support for the ARM1176 tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_A9MP - bool "Support Multicore Cortex-A9 Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 - help - Enable support for the Cortex-A9MPCore tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_ARM11MP - bool "Support ARM11MPCore Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - select HAVE_SMP - help - Enable support for the ARM11MPCore tile fitted to the Realview(R) - Emulation Baseboard platform. - -config MACH_REALVIEW_PB11MP - bool "Support RealView(R) Platform Baseboard for ARM11MPCore" - depends on ARCH_MULTI_V6 - select HAVE_SMP - help - Include support for the ARM(R) RealView(R) Platform Baseboard for - the ARM11MPCore. This platform has an on-board ARM11MPCore and has - support for PCI-E and Compact Flash. - -# ARMv6 CPU without K extensions, but does have the new exclusive ops -config MACH_REALVIEW_PB1176 - bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" - depends on ARCH_MULTI_V6 - select CPU_V6 - select HAVE_TCM - help - Include support for the ARM(R) RealView(R) Platform Baseboard for - ARM1176JZF-S. - -config MACH_REALVIEW_PBA8 - bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" - depends on ARCH_MULTI_V7 - help - Include support for the ARM(R) RealView Platform Baseboard for - Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has - support for PCI-E and Compact Flash. - -config MACH_REALVIEW_PBX - bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" - depends on ARCH_MULTI_V7 - select ZONE_DMA - help - Include support for the ARM(R) RealView(R) Platform Baseboard - Explore. - -endif diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile deleted file mode 100644 index e259091591b8..000000000000 --- a/arch/arm/mach-realview/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include - -obj-y += realview-dt.o -obj-$(CONFIG_SMP) += platsmp-dt.o diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index f78a1d358031..94b492c12e8d 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -16,3 +16,311 @@ config ARCH_VERSATILE help This enables support for ARM Ltd Versatile board. +menuconfig ARCH_INTEGRATOR + bool "ARM Ltd. Integrator family" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 + select ARM_AMBA + select CMA + select DMA_CMA + select HAVE_TCM + select CLK_ICST + select MFD_SYSCON + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VERSATILE + select POWER_SUPPLY + select SOC_INTEGRATOR_CM + select VERSATILE_FPGA_IRQ + help + Support for ARM's Integrator platform. + +if ARCH_INTEGRATOR + +config ARCH_INTEGRATOR_AP + bool "Support Integrator/AP and Integrator/PP2 platforms" + select INTEGRATOR_AP_TIMER + select SERIAL_AMBA_PL010 if TTY + select SERIAL_AMBA_PL010_CONSOLE if TTY + select SOC_BUS + help + Include support for the ARM(R) Integrator/AP and + Integrator/PP2 platforms. + +config INTEGRATOR_IMPD1 + bool "Include support for Integrator/IM-PD1" + depends on ARCH_INTEGRATOR_AP + select ARM_VIC + select GPIO_PL061 + select GPIOLIB + select REGULATOR + select REGULATOR_FIXED_VOLTAGE + help + The IM-PD1 is an add-on logic module for the Integrator which + allows ARM(R) Ltd PrimeCells to be developed and evaluated. + The IM-PD1 can be found on the Integrator/PP2 platform. + +config INTEGRATOR_CM720T + bool "Integrator/CM720T core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V4T + select CPU_ARM720T + +config INTEGRATOR_CM920T + bool "Integrator/CM920T core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V4T + select CPU_ARM920T + +config INTEGRATOR_CM922T_XA10 + bool "Integrator/CM922T-XA10 core module" + depends on ARCH_MULTI_V4T + depends on ARCH_INTEGRATOR_AP + select CPU_ARM922T + +config INTEGRATOR_CM926EJS + bool "Integrator/CM926EJ-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM926T + +config INTEGRATOR_CM10200E_REV0 + bool "Integrator/CM10200E rev.0 core module" + depends on ARCH_INTEGRATOR_AP && n + depends on ARCH_MULTI_V5 + select CPU_ARM1020 + +config INTEGRATOR_CM10200E + bool "Integrator/CM10200E core module" + depends on ARCH_INTEGRATOR_AP && n + depends on ARCH_MULTI_V5 + select CPU_ARM1020E + +config INTEGRATOR_CM10220E + bool "Integrator/CM10220E core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM1022 + +config INTEGRATOR_CM1026EJS + bool "Integrator/CM1026EJ-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM1026 + +config INTEGRATOR_CM1136JFS + bool "Integrator/CM1136JF-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V6 + select CPU_V6 + +config ARCH_INTEGRATOR_CP + bool "Support Integrator/CP platform" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + select ARM_TIMER_SP804 + select SERIAL_AMBA_PL011 if TTY + select SERIAL_AMBA_PL011_CONSOLE if TTY + select SOC_BUS + help + Include support for the ARM(R) Integrator CP platform. + +config INTEGRATOR_CT926 + bool "Integrator/CT926 (ARM926EJ-S) core tile" + depends on ARCH_INTEGRATOR_CP + depends on ARCH_MULTI_V5 + select CPU_ARM926T + +config INTEGRATOR_CTB36 + bool "Integrator/CTB36 (ARM1136JF-S) core tile" + depends on ARCH_INTEGRATOR_CP + depends on ARCH_MULTI_V6 + select CPU_V6 + +config ARCH_CINTEGRATOR + depends on ARCH_INTEGRATOR_CP + def_bool y + +endif + +menuconfig ARCH_REALVIEW + bool "ARM Ltd. RealView family" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_TIMER_SP804 + select CLK_SP810 + select GPIO_PL061 if GPIOLIB + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_PATA_PLATFORM + select HAVE_TCM + select CLK_ICST + select MACH_REALVIEW_EB if ARCH_MULTI_V5 + select MFD_SYSCON + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VERSATILE + select POWER_SUPPLY + select SOC_REALVIEW + help + This enables support for ARM Ltd RealView boards. + +if ARCH_REALVIEW + +config MACH_REALVIEW_EB + bool "Support RealView(R) Emulation Baseboard" + select ARM_GIC + select CPU_ARM926T if ARCH_MULTI_V5 + help + Include support for the ARM(R) RealView(R) Emulation Baseboard + platform. On an ARMv5 kernel, this will include support for + the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least + one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore + core tile options should be enabled. + +config REALVIEW_EB_ARM1136 + bool "Support ARM1136J(F)-S Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + select CPU_V6 + help + Enable support for the ARM1136 tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_ARM1176 + bool "Support ARM1176JZ(F)-S Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + help + Enable support for the ARM1176 tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_A9MP + bool "Support Multicore Cortex-A9 Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 + help + Enable support for the Cortex-A9MPCore tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_ARM11MP + bool "Support ARM11MPCore Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + select HAVE_SMP + help + Enable support for the ARM11MPCore tile fitted to the Realview(R) + Emulation Baseboard platform. + +config MACH_REALVIEW_PB11MP + bool "Support RealView(R) Platform Baseboard for ARM11MPCore" + depends on ARCH_MULTI_V6 + select HAVE_SMP + help + Include support for the ARM(R) RealView(R) Platform Baseboard for + the ARM11MPCore. This platform has an on-board ARM11MPCore and has + support for PCI-E and Compact Flash. + +# ARMv6 CPU without K extensions, but does have the new exclusive ops +config MACH_REALVIEW_PB1176 + bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" + depends on ARCH_MULTI_V6 + select CPU_V6 + select HAVE_TCM + help + Include support for the ARM(R) RealView(R) Platform Baseboard for + ARM1176JZF-S. + +config MACH_REALVIEW_PBA8 + bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" + depends on ARCH_MULTI_V7 + help + Include support for the ARM(R) RealView Platform Baseboard for + Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has + support for PCI-E and Compact Flash. + +config MACH_REALVIEW_PBX + bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" + depends on ARCH_MULTI_V7 + select ZONE_DMA + help + Include support for the ARM(R) RealView(R) Platform Baseboard + Explore. + +endif + +menuconfig ARCH_VEXPRESS + bool "ARM Ltd. Versatile Express family" + depends on ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN + select ARM_AMBA + select ARM_GIC + select ARM_GLOBAL_TIMER + select ARM_TIMER_SP804 + select GPIOLIB + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_PATA_PLATFORM + select CLK_ICST + select NO_IOPORT_MAP + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VEXPRESS + select POWER_SUPPLY + select REGULATOR if MMC_ARMMMCI + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select VEXPRESS_CONFIG + help + This option enables support for systems using Cortex processor based + ARM core and logic (FPGA) tiles on the Versatile Express motherboard, + for example: + + - CoreTile Express A5x2 (V2P-CA5s) + - CoreTile Express A9x4 (V2P-CA9) + - CoreTile Express A15x2 (V2P-CA15) + - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs + (Soft Macrocell Models) + - Versatile Express RTSMs (Models) + + You must boot using a Flattened Device Tree in order to use these + platforms. The traditional (ATAGs) boot method is not usable on + these boards with this option. + +if ARCH_VEXPRESS + +config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA + bool "Enable A5 and A9 only errata work-arounds" + default y + select ARM_ERRATA_643719 if SMP + select ARM_ERRATA_720789 + select PL310_ERRATA_753970 if CACHE_L2X0 + help + Provides common dependencies for Versatile Express platforms + based on Cortex-A5 and Cortex-A9 processors. In order to + build a working kernel, you must also enable relevant core + tile support or Flattened Device Tree based support options. + +config ARCH_VEXPRESS_DCSCB + bool "Dual Cluster System Control Block (DCSCB) support" + depends on MCPM + select ARM_CCI400_PORT_CTRL + help + Support for the Dual Cluster System Configuration Block (DCSCB). + This is needed to provide CPU and cluster power management + on RTSM implementing big.LITTLE. + +config ARCH_VEXPRESS_SPC + bool "Versatile Express Serial Power Controller (SPC)" + select PM_OPP + help + The TC2 (A15x2 A7x3) versatile express core tile integrates a logic + block called Serial Power Controller (SPC) that provides the interface + between the dual cluster test-chip and the M3 microcontroller that + carries out power management. + +config ARCH_VEXPRESS_TC2_PM + bool "Versatile Express TC2 power management" + depends on MCPM + select ARM_CCI400_PORT_CTRL + select ARCH_VEXPRESS_SPC + select ARM_CPU_SUSPEND + help + Support for CPU and cluster power management on Versatile Express + with a TC2 (A15x2 A7x3) big.LITTLE core tile. + +endif diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile index 2b907718d467..27d712bcf1af 100644 --- a/arch/arm/mach-versatile/Makefile +++ b/arch/arm/mach-versatile/Makefile @@ -3,4 +3,34 @@ # Makefile for the linux kernel. # -obj-y := versatile_dt.o +# versatile +obj-$(CONFIG_ARCH_VERSATILE) += versatile.o + +# integrator +obj-$(CONFIG_ARCH_INTEGRATOR) += integrator.o +obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o +obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o + +# realview +obj-$(CONFIG_ARCH_REALVIEW) += realview.o + +# vexpress +obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o +CFLAGS_dcscb.o += -march=armv7-a +CFLAGS_REMOVE_dcscb.o = -pg +obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o +CFLAGS_REMOVE_spc.o = -pg +obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o +CFLAGS_tc2_pm.o += -march=armv7-a +CFLAGS_REMOVE_tc2_pm.o = -pg + +# mps2 +obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o + +ifdef CONFIG_SMP +obj-y += headsmp.o platsmp.o +obj-$(CONFIG_ARCH_REALVIEW) += platsmp-realview.o +obj-$(CONFIG_ARCH_VEXPRESS) += platsmp-vexpress.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +endif diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-versatile/Makefile.boot similarity index 100% rename from arch/arm/mach-vexpress/Makefile.boot rename to arch/arm/mach-versatile/Makefile.boot diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-versatile/dcscb.c similarity index 97% rename from arch/arm/mach-vexpress/dcscb.c rename to arch/arm/mach-versatile/dcscb.c index a0554d7d04f7..866270e7f271 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-versatile/dcscb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block + * dcscb.c - Dual Cluster System Configuration Block * * Created by: Nicolas Pitre, May 2012 * Copyright: (C) 2012-2013 Linaro Limited @@ -20,7 +20,7 @@ #include #include -#include "core.h" +#include "vexpress.h" #define RST_HOLD0 0x0 #define RST_HOLD1 0x4 diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-versatile/dcscb_setup.S similarity index 95% rename from arch/arm/mach-vexpress/dcscb_setup.S rename to arch/arm/mach-versatile/dcscb_setup.S index 0614b2ebd354..92d1fd9d7f6a 100644 --- a/arch/arm/mach-vexpress/dcscb_setup.S +++ b/arch/arm/mach-versatile/dcscb_setup.S @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * arch/arm/include/asm/dcscb_setup.S - * * Created by: Dave Martin, 2012-06-22 * Copyright: (C) 2012-2013 Linaro Limited */ diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/mach-versatile/headsmp.S similarity index 94% rename from arch/arm/plat-versatile/headsmp.S rename to arch/arm/mach-versatile/headsmp.S index 09d9fc30c8ca..99c32db412ae 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/mach-versatile/headsmp.S @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * linux/arch/arm/plat-versatile/headsmp.S - * * Copyright (c) 2003 ARM Limited * All Rights Reserved */ diff --git a/arch/arm/plat-versatile/hotplug.c b/arch/arm/mach-versatile/hotplug.c similarity index 98% rename from arch/arm/plat-versatile/hotplug.c rename to arch/arm/mach-versatile/hotplug.c index 2e9dca38bec0..5a152175578b 100644 --- a/arch/arm/plat-versatile/hotplug.c +++ b/arch/arm/mach-versatile/hotplug.c @@ -15,7 +15,7 @@ #include #include -#include +#include "platsmp.h" static inline void versatile_immitation_enter_lowpower(unsigned int actrl_mask) { diff --git a/arch/arm/mach-integrator/cm.h b/arch/arm/mach-versatile/integrator-cm.h similarity index 100% rename from arch/arm/mach-integrator/cm.h rename to arch/arm/mach-versatile/integrator-cm.h diff --git a/arch/arm/mach-integrator/hardware.h b/arch/arm/mach-versatile/integrator-hardware.h similarity index 100% rename from arch/arm/mach-integrator/hardware.h rename to arch/arm/mach-versatile/integrator-hardware.h diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-versatile/integrator.c similarity index 95% rename from arch/arm/mach-integrator/core.c rename to arch/arm/mach-versatile/integrator.c index 0fe5e1dc9d89..fdf9c4db08a7 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-versatile/integrator.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/mach-integrator/core.c - * * Copyright (C) 2000-2003 Deep Blue Solutions Ltd */ #include @@ -26,9 +24,9 @@ #include #include -#include "hardware.h" -#include "cm.h" -#include "common.h" +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" static DEFINE_RAW_SPINLOCK(cm_lock); static void __iomem *cm_base; diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-versatile/integrator.h similarity index 100% rename from arch/arm/mach-integrator/common.h rename to arch/arm/mach-versatile/integrator.h diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c similarity index 97% rename from arch/arm/mach-integrator/integrator_ap.c rename to arch/arm/mach-versatile/integrator_ap.c index 58b02cbbea72..44a69cc69376 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-versatile/integrator_ap.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * linux/arch/arm/mach-integrator/integrator_ap.c - * * Copyright (C) 2000-2003 Deep Blue Solutions Ltd */ #include @@ -20,9 +18,9 @@ #include #include -#include "hardware.h" -#include "cm.h" -#include "common.h" +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" /* Regmap to the AP system controller */ static struct regmap *ap_syscon_map; diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-versatile/integrator_cp.c similarity index 96% rename from arch/arm/mach-integrator/integrator_cp.c rename to arch/arm/mach-versatile/integrator_cp.c index b7eb4038798b..2ed4ded56b3f 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-versatile/integrator_cp.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/mach-integrator/integrator_cp.c - * * Copyright (C) 2003 Deep Blue Solutions Ltd */ #include @@ -18,9 +16,9 @@ #include #include -#include "hardware.h" -#include "cm.h" -#include "common.h" +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" /* Base address to the core module header */ static struct regmap *cm_map; diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-versatile/platsmp-realview.c similarity index 98% rename from arch/arm/mach-realview/platsmp-dt.c rename to arch/arm/mach-versatile/platsmp-realview.c index 5ae783767a5d..5d363385c801 100644 --- a/arch/arm/mach-realview/platsmp-dt.c +++ b/arch/arm/mach-versatile/platsmp-realview.c @@ -13,7 +13,7 @@ #include #include -#include +#include "platsmp.h" #define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-versatile/platsmp-vexpress.c similarity index 96% rename from arch/arm/mach-vexpress/platsmp.c rename to arch/arm/mach-versatile/platsmp-vexpress.c index 99c93124aa68..1ee3c45e71c9 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-versatile/platsmp-vexpress.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/mach-vexpress/platsmp.c - * * Copyright (C) 2002 ARM Ltd. * All Rights Reserved */ @@ -16,9 +14,8 @@ #include #include -#include - -#include "core.h" +#include "platsmp.h" +#include "vexpress.h" bool __init vexpress_smp_init_ops(void) { diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/mach-versatile/platsmp.c similarity index 97% rename from arch/arm/plat-versatile/platsmp.c rename to arch/arm/mach-versatile/platsmp.c index 3567296cec2a..fa7378321e23 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/mach-versatile/platsmp.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/plat-versatile/platsmp.c - * * Copyright (C) 2002 ARM Ltd. * All Rights Reserved * @@ -20,7 +18,7 @@ #include #include -#include +#include "platsmp.h" /* * versatile_cpu_release controls the release of CPUs from the holding diff --git a/arch/arm/plat-versatile/include/plat/platsmp.h b/arch/arm/mach-versatile/platsmp.h similarity index 87% rename from arch/arm/plat-versatile/include/plat/platsmp.h rename to arch/arm/mach-versatile/platsmp.h index 500605f48b80..171a0ab72220 100644 --- a/arch/arm/plat-versatile/include/plat/platsmp.h +++ b/arch/arm/mach-versatile/platsmp.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * linux/arch/arm/plat-versatile/include/plat/platsmp.h - * * Copyright (C) 2011 ARM Ltd. * All Rights Reserved */ diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-versatile/realview.c similarity index 100% rename from arch/arm/mach-realview/realview-dt.c rename to arch/arm/mach-versatile/realview.c diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-versatile/spc.c similarity index 100% rename from arch/arm/mach-vexpress/spc.c rename to arch/arm/mach-versatile/spc.c diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-versatile/spc.h similarity index 100% rename from arch/arm/mach-vexpress/spc.h rename to arch/arm/mach-versatile/spc.h diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-versatile/tc2_pm.c similarity index 99% rename from arch/arm/mach-vexpress/tc2_pm.c rename to arch/arm/mach-versatile/tc2_pm.c index e96c42ae3602..0fe78da0c109 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-versatile/tc2_pm.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support - * * Created by: Nicolas Pitre, October 2012 * Copyright: (C) 2012-2013 Linaro Limited * diff --git a/arch/arm/mach-vexpress/v2m-mps2.c b/arch/arm/mach-versatile/v2m-mps2.c similarity index 100% rename from arch/arm/mach-vexpress/v2m-mps2.c rename to arch/arm/mach-versatile/v2m-mps2.c diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-versatile/v2m.c similarity index 97% rename from arch/arm/mach-vexpress/v2m.c rename to arch/arm/mach-versatile/v2m.c index ffe7c7a85ae9..79afdf2a90b6 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-versatile/v2m.c @@ -3,7 +3,7 @@ #include #include -#include "core.h" +#include "vexpress.h" #define SYS_FLAGSSET 0x030 #define SYS_FLAGSCLR 0x034 diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile.c similarity index 100% rename from arch/arm/mach-versatile/versatile_dt.c rename to arch/arm/mach-versatile/versatile.c diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-versatile/vexpress.h similarity index 100% rename from arch/arm/mach-vexpress/core.h rename to arch/arm/mach-versatile/vexpress.h diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig deleted file mode 100644 index 2e6aff5a0f17..000000000000 --- a/arch/arm/mach-vexpress/Kconfig +++ /dev/null @@ -1,81 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_VEXPRESS - bool "ARM Ltd. Versatile Express family" - depends on ARCH_MULTI_V7 - select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_AMBA - select ARM_GIC - select ARM_GLOBAL_TIMER - select ARM_TIMER_SP804 - select GPIOLIB - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_PATA_PLATFORM - select CLK_ICST - select NO_IOPORT_MAP - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VEXPRESS - select POWER_SUPPLY - select REGULATOR if MMC_ARMMMCI - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select VEXPRESS_CONFIG - help - This option enables support for systems using Cortex processor based - ARM core and logic (FPGA) tiles on the Versatile Express motherboard, - for example: - - - CoreTile Express A5x2 (V2P-CA5s) - - CoreTile Express A9x4 (V2P-CA9) - - CoreTile Express A15x2 (V2P-CA15) - - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs - (Soft Macrocell Models) - - Versatile Express RTSMs (Models) - - You must boot using a Flattened Device Tree in order to use these - platforms. The traditional (ATAGs) boot method is not usable on - these boards with this option. - -if ARCH_VEXPRESS - -config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA - bool "Enable A5 and A9 only errata work-arounds" - default y - select ARM_ERRATA_643719 if SMP - select ARM_ERRATA_720789 - select PL310_ERRATA_753970 if CACHE_L2X0 - help - Provides common dependencies for Versatile Express platforms - based on Cortex-A5 and Cortex-A9 processors. In order to - build a working kernel, you must also enable relevant core - tile support or Flattened Device Tree based support options. - -config ARCH_VEXPRESS_DCSCB - bool "Dual Cluster System Control Block (DCSCB) support" - depends on MCPM - select ARM_CCI400_PORT_CTRL - help - Support for the Dual Cluster System Configuration Block (DCSCB). - This is needed to provide CPU and cluster power management - on RTSM implementing big.LITTLE. - -config ARCH_VEXPRESS_SPC - bool "Versatile Express Serial Power Controller (SPC)" - select PM_OPP - help - The TC2 (A15x2 A7x3) versatile express core tile integrates a logic - block called Serial Power Controller (SPC) that provides the interface - between the dual cluster test-chip and the M3 microcontroller that - carries out power management. - -config ARCH_VEXPRESS_TC2_PM - bool "Versatile Express TC2 power management" - depends on MCPM - select ARM_CCI400_PORT_CTRL - select ARCH_VEXPRESS_SPC - select ARM_CPU_SUSPEND - help - Support for CPU and cluster power management on Versatile Express - with a TC2 (A15x2 A7x3) big.LITTLE core tile. - -endif diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile deleted file mode 100644 index 3651a1ed0f2b..000000000000 --- a/arch/arm/mach-vexpress/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \ - -I$(srctree)/arch/arm/plat-versatile/include - -obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o -obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o -CFLAGS_dcscb.o += -march=armv7-a -CFLAGS_REMOVE_dcscb.o = -pg -obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o -CFLAGS_REMOVE_spc.o = -pg -obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o -CFLAGS_tc2_pm.o += -march=armv7-a -CFLAGS_REMOVE_tc2_pm.o = -pg -obj-$(CONFIG_SMP) += platsmp.o - -obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile deleted file mode 100644 index 5de44a57c4de..000000000000 --- a/arch/arm/plat-versatile/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include - -obj-$(CONFIG_SMP) += headsmp.o platsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o From 482c27273f52ad336e8d076f96f91b358dcb7d0c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 22 Oct 2019 10:42:51 +0200 Subject: [PATCH 0016/1268] ARM: ep93xx: renumber interrupts With the move to irq domains, no irqchip must start at number 0, so shift all the hardwired IRQ numbers by one. Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/mach-ep93xx/core.c | 4 +- arch/arm/mach-ep93xx/include/mach/irqs.h | 122 ++++++++++++----------- 2 files changed, 65 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index a3b4e843456a..e4569a5acc3f 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -75,8 +75,8 @@ void __init ep93xx_map_io(void) *************************************************************************/ void __init ep93xx_init_irq(void) { - vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); - vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0); } diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h index 244daf83ce6d..60c69c4ed7e1 100644 --- a/arch/arm/mach-ep93xx/include/mach/irqs.h +++ b/arch/arm/mach-ep93xx/include/mach/irqs.h @@ -6,69 +6,73 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#define IRQ_EP93XX_COMMRX 2 -#define IRQ_EP93XX_COMMTX 3 -#define IRQ_EP93XX_TIMER1 4 -#define IRQ_EP93XX_TIMER2 5 -#define IRQ_EP93XX_AACINTR 6 -#define IRQ_EP93XX_DMAM2P0 7 -#define IRQ_EP93XX_DMAM2P1 8 -#define IRQ_EP93XX_DMAM2P2 9 -#define IRQ_EP93XX_DMAM2P3 10 -#define IRQ_EP93XX_DMAM2P4 11 -#define IRQ_EP93XX_DMAM2P5 12 -#define IRQ_EP93XX_DMAM2P6 13 -#define IRQ_EP93XX_DMAM2P7 14 -#define IRQ_EP93XX_DMAM2P8 15 -#define IRQ_EP93XX_DMAM2P9 16 -#define IRQ_EP93XX_DMAM2M0 17 -#define IRQ_EP93XX_DMAM2M1 18 -#define IRQ_EP93XX_GPIO0MUX 19 -#define IRQ_EP93XX_GPIO1MUX 20 -#define IRQ_EP93XX_GPIO2MUX 21 -#define IRQ_EP93XX_GPIO3MUX 22 -#define IRQ_EP93XX_UART1RX 23 -#define IRQ_EP93XX_UART1TX 24 -#define IRQ_EP93XX_UART2RX 25 -#define IRQ_EP93XX_UART2TX 26 -#define IRQ_EP93XX_UART3RX 27 -#define IRQ_EP93XX_UART3TX 28 -#define IRQ_EP93XX_KEY 29 -#define IRQ_EP93XX_TOUCH 30 +#define IRQ_EP93XX_VIC0 1 + +#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) +#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) +#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) +#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) +#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) +#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) +#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) +#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) +#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) +#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) +#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) +#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) +#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) +#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) +#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc -#define IRQ_EP93XX_EXT0 32 -#define IRQ_EP93XX_EXT1 33 -#define IRQ_EP93XX_EXT2 34 -#define IRQ_EP93XX_64HZ 35 -#define IRQ_EP93XX_WATCHDOG 36 -#define IRQ_EP93XX_RTC 37 -#define IRQ_EP93XX_IRDA 38 -#define IRQ_EP93XX_ETHERNET 39 -#define IRQ_EP93XX_EXT3 40 -#define IRQ_EP93XX_PROG 41 -#define IRQ_EP93XX_1HZ 42 -#define IRQ_EP93XX_VSYNC 43 -#define IRQ_EP93XX_VIDEO_FIFO 44 -#define IRQ_EP93XX_SSP1RX 45 -#define IRQ_EP93XX_SSP1TX 46 -#define IRQ_EP93XX_GPIO4MUX 47 -#define IRQ_EP93XX_GPIO5MUX 48 -#define IRQ_EP93XX_GPIO6MUX 49 -#define IRQ_EP93XX_GPIO7MUX 50 -#define IRQ_EP93XX_TIMER3 51 -#define IRQ_EP93XX_UART1 52 -#define IRQ_EP93XX_SSP 53 -#define IRQ_EP93XX_UART2 54 -#define IRQ_EP93XX_UART3 55 -#define IRQ_EP93XX_USB 56 -#define IRQ_EP93XX_ETHERNET_PME 57 -#define IRQ_EP93XX_DSP 58 -#define IRQ_EP93XX_GPIO_AB 59 -#define IRQ_EP93XX_SAI 60 +#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) + +#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) +#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) +#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) +#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) +#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) +#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) +#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) +#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) +#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) +#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) +#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) +#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) +#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) +#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) +#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) +#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) +#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) +#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) +#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) +#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) +#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) +#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) +#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) +#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) +#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) +#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) +#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) +#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) +#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff -#define NR_EP93XX_IRQS (64 + 24) +#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) #define EP93XX_BOARD_IRQS 32 From 36f1a4ae6b60a9fbd9a35a3b257dc6e53b5feff1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 20 Sep 2019 10:10:03 +0200 Subject: [PATCH 0017/1268] ARM: ep93xx: enable SPARSE_IRQ Without CONFIG_SPARSE_IRQ, we rely on mach/irqs.h to define NR_IRQS globally. Do the minimal conversion by setting .nr_irqs in each machine descriptor. Only the vision_ep9307 machine has extra IRQs for GPIOs, so make .nr_irqs the original value there, while using the plain NR_EP93XX_IRQS everywhere else. Cc: Hartley Sweeten Cc: Hubert Feurstein Cc: Lukasz Majewski Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 ++ arch/arm/mach-ep93xx/adssphere.c | 1 + arch/arm/mach-ep93xx/core.c | 1 + arch/arm/mach-ep93xx/edb93xx.c | 8 ++++++++ arch/arm/mach-ep93xx/gesbc9312.c | 1 + arch/arm/mach-ep93xx/{include/mach => }/irqs.h | 7 ------- arch/arm/mach-ep93xx/micro9.c | 4 ++++ arch/arm/mach-ep93xx/simone.c | 1 + arch/arm/mach-ep93xx/snappercl15.c | 1 + arch/arm/mach-ep93xx/soc.h | 1 + arch/arm/mach-ep93xx/ts72xx.c | 3 ++- arch/arm/mach-ep93xx/vision_ep9307.c | 1 + 12 files changed, 23 insertions(+), 8 deletions(-) rename arch/arm/mach-ep93xx/{include/mach => }/irqs.h (96%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31f024e6e925..5177e54cc14c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -358,6 +358,8 @@ config ARCH_EP93XX select CPU_ARM920T select GPIOLIB select COMMON_CLK + select IRQ_DOMAIN + select SPARSE_IRQ help This enables support for the Cirrus EP93xx series of CPUs. diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 8d5e349a7a6d..0c48d3c5b8e7 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -32,6 +32,7 @@ static void __init adssphere_init_machine(void) MACHINE_START(ADSSPHERE, "ADS Sphere board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index e4569a5acc3f..2d58e273c96d 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -47,6 +47,7 @@ #include #include "soc.h" +#include "irqs.h" /************************************************************************* * Static I/O mappings that are needed for all EP93xx platforms diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index af0e22471ebd..4b90899a66e9 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -243,6 +243,7 @@ static void __init edb93xx_init_machine(void) MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -255,6 +256,7 @@ MACHINE_END MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") /* Maintainer: George Kashperko */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -267,6 +269,7 @@ MACHINE_END MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -279,6 +282,7 @@ MACHINE_END MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") /* Maintainer: Herbert Valerio Riedel */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -291,6 +295,7 @@ MACHINE_END MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -303,6 +308,7 @@ MACHINE_END MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") /* Maintainer: Toufeeq Hussain */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -315,6 +321,7 @@ MACHINE_END MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -327,6 +334,7 @@ MACHINE_END MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index d7f9890321eb..0b7043e3e178 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -32,6 +32,7 @@ static void __init gesbc9312_init_machine(void) MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/irqs.h similarity index 96% rename from arch/arm/mach-ep93xx/include/mach/irqs.h rename to arch/arm/mach-ep93xx/irqs.h index 60c69c4ed7e1..353201b90c66 100644 --- a/arch/arm/mach-ep93xx/include/mach/irqs.h +++ b/arch/arm/mach-ep93xx/irqs.h @@ -1,8 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/irqs.h - */ - #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H @@ -77,7 +73,4 @@ #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) #define EP93XX_BOARD_IRQS 32 -#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS) - - #endif diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index e6ead8ded6ee..c121c459aa17 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -76,6 +76,7 @@ static void __init micro9_init_machine(void) MACHINE_START(MICRO9, "Contec Micro9-High") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -88,6 +89,7 @@ MACHINE_END MACHINE_START(MICRO9M, "Contec Micro9-Mid") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -100,6 +102,7 @@ MACHINE_END MACHINE_START(MICRO9L, "Contec Micro9-Lite") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -112,6 +115,7 @@ MACHINE_END MACHINE_START(MICRO9S, "Contec Micro9-Slim") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 5291053023b2..569e72413561 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -119,6 +119,7 @@ static void __init simone_init_machine(void) MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index e200d69471e9..1dfb725671b1 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -153,6 +153,7 @@ static void __init snappercl15_init_machine(void) MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index 94ef7f275f94..f0986e288d19 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h @@ -10,6 +10,7 @@ #define _EP93XX_SOC_H #include +#include "irqs.h" /* * EP93xx Physical Memory Map: diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 12eff8c8074d..e70bac011407 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -22,7 +22,6 @@ #include "gpio-ep93xx.h" #include "hardware.h" -#include #include #include @@ -350,6 +349,7 @@ static void __init ts72xx_init_machine(void) MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -413,6 +413,7 @@ static void __init bk3_init_machine(void) MACHINE_START(BK3, "Liebherr controller BK3.1") /* Maintainer: Lukasz Majewski */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index e46281e60bf7..30d9cf3791eb 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -302,6 +302,7 @@ static void __init vision_init_machine(void) MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, .map_io = vision_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, From 4e5f36f84614ce59b140ae6706603d76e6e0cdbe Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 20 Sep 2019 10:18:31 +0200 Subject: [PATCH 0018/1268] ARM: ep93xx: make mach/ep93xx-regs.h local Nothing relies on it outside of arch/arm/mach-ep93xx/, so just move it there. Cc: Hartley Sweeten Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/mach-ep93xx/{include/mach => }/ep93xx-regs.h | 4 ---- arch/arm/mach-ep93xx/gpio-ep93xx.h | 2 +- arch/arm/mach-ep93xx/include/mach/uncompress.h | 1 - arch/arm/mach-ep93xx/soc.h | 2 +- 4 files changed, 2 insertions(+), 7 deletions(-) rename arch/arm/mach-ep93xx/{include/mach => }/ep93xx-regs.h (94%) diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93xx-regs.h similarity index 94% rename from arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h rename to arch/arm/mach-ep93xx/ep93xx-regs.h index 6839ea032e58..8fa3646de0a4 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/ep93xx-regs.h @@ -1,8 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h - */ - #ifndef __ASM_ARCH_EP93XX_REGS_H #define __ASM_ARCH_EP93XX_REGS_H diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio-ep93xx.h index 242af4a401ea..7b46eb7e5507 100644 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ b/arch/arm/mach-ep93xx/gpio-ep93xx.h @@ -4,7 +4,7 @@ #ifndef __GPIO_EP93XX_H #define __GPIO_EP93XX_H -#include +#include "ep93xx-regs.h" #define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index b3ec1db988db..e20bcab702b2 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -5,7 +5,6 @@ * Copyright (C) 2006 Lennert Buytenhek */ -#include #include static unsigned char __raw_readb(unsigned int ptr) diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index f0986e288d19..3245ebbd5069 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h @@ -9,7 +9,7 @@ #ifndef _EP93XX_SOC_H #define _EP93XX_SOC_H -#include +#include "ep93xx-regs.h" #include "irqs.h" /* From 0361c7e504b1fa3c2901643088e2f29c0354ab31 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 1 Apr 2022 15:58:09 +0200 Subject: [PATCH 0019/1268] ARM: ep93xx: multiplatform support With the clock support and the interrupts out of the way, ep93xx can be compiled into the same kernel image as the other ARMv4/v5 platforms. The last obstacle are the two workarounds for broken boot loaders that require us to re-initialize the ethernet controller and/or the watchdog on certain machines. Move this code into the decompressor sources directly, checking for each possibly affected machine individually. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 16 ----- .../compressed/misc-ep93xx.h} | 69 +++++++++---------- arch/arm/boot/compressed/misc.c | 4 ++ arch/arm/configs/ep93xx_defconfig | 2 + arch/arm/mach-ep93xx/Kconfig | 12 ++++ 5 files changed, 51 insertions(+), 52 deletions(-) rename arch/arm/{mach-ep93xx/include/mach/uncompress.h => boot/compressed/misc-ep93xx.h} (51%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5177e54cc14c..2bd611beefe1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -347,22 +347,6 @@ config ARCH_MULTIPLATFORM select SPARSE_IRQ select USE_OF -config ARCH_EP93XX - bool "EP93xx-based" - select ARCH_SPARSEMEM_ENABLE - select ARM_AMBA - imply ARM_PATCH_PHYS_VIRT - select ARM_VIC - select AUTO_ZRELADDR - select CLKSRC_MMIO - select CPU_ARM920T - select GPIOLIB - select COMMON_CLK - select IRQ_DOMAIN - select SPARSE_IRQ - help - This enables support for the Cirrus EP93xx series of CPUs. - config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/boot/compressed/misc-ep93xx.h similarity index 51% rename from arch/arm/mach-ep93xx/include/mach/uncompress.h rename to arch/arm/boot/compressed/misc-ep93xx.h index e20bcab702b2..3dc942589cba 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -1,54 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * arch/arm/mach-ep93xx/include/mach/uncompress.h - * * Copyright (C) 2006 Lennert Buytenhek */ #include -static unsigned char __raw_readb(unsigned int ptr) -{ - return *((volatile unsigned char *)ptr); -} - -static unsigned int __raw_readl(unsigned int ptr) +static inline unsigned int __raw_readl(unsigned int ptr) { return *((volatile unsigned int *)ptr); } -static void __raw_writeb(unsigned char value, unsigned int ptr) +static inline void __raw_writeb(unsigned char value, unsigned int ptr) { *((volatile unsigned char *)ptr) = value; } -static void __raw_writel(unsigned int value, unsigned int ptr) +static inline void __raw_writel(unsigned int value, unsigned int ptr) { *((volatile unsigned int *)ptr) = value; } -#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00) -#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18) -#define UART_FLAG_TXFF 0x20 - -static inline void putc(int c) -{ - int i; - - for (i = 0; i < 10000; i++) { - /* Transmit fifo not full? */ - if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) - break; - } - - __raw_writeb(c, PHYS_UART_DATA); -} - -static inline void flush(void) -{ -} - - /* * Some bootloaders don't turn off DMA from the ethernet MAC before * jumping to linux, which means that we might end up with bits of RX @@ -58,7 +29,7 @@ static inline void flush(void) #define PHYS_ETH_SELF_CTL 0x80010020 #define ETH_SELF_CTL_RESET 0x00000001 -static void ethernet_reset(void) +static inline void ep93xx_ethernet_reset(void) { unsigned int v; @@ -75,15 +46,41 @@ static void ethernet_reset(void) #define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 #define TS72XX_WDT_FEED_VAL 0x05 -static void __maybe_unused ts72xx_watchdog_disable(void) +static inline void __maybe_unused ts72xx_watchdog_disable(void) { __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); } -static void arch_decomp_setup(void) +static inline void ep93xx_decomp_setup(void) { if (machine_is_ts72xx()) ts72xx_watchdog_disable(); - ethernet_reset(); + + if (machine_is_adssphere() || + machine_is_edb9301() || + machine_is_edb9302() || + machine_is_edb9302a() || + machine_is_edb9302a() || + machine_is_edb9307() || + machine_is_edb9307a() || + machine_is_edb9307a() || + machine_is_edb9312() || + machine_is_edb9315() || + machine_is_edb9315a() || + machine_is_edb9315a() || + machine_is_gesbc9312() || + machine_is_micro9() || + machine_is_micro9l() || + machine_is_micro9m() || + machine_is_micro9s() || + machine_is_micro9m() || + machine_is_micro9l() || + machine_is_micro9s() || + machine_is_sim_one() || + machine_is_snapper_cl15() || + machine_is_ts72xx() || + machine_is_bk3() || + machine_is_vision_ep9307()) + ep93xx_ethernet_reset(); } diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index c3c66ff2d696..cb2e069dc73f 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -23,6 +23,7 @@ unsigned int __machine_arch_type; #include #include #include "misc.h" +#include "misc-ep93xx.h" static void putstr(const char *ptr); @@ -143,6 +144,9 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, free_mem_end_ptr = free_mem_ptr_end_p; __machine_arch_type = arch_id; +#ifdef CONFIG_ARCH_EP93XX + ep93xx_decomp_setup(); +#endif arch_decomp_setup(); putstr("Uncompressing Linux..."); diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 88d5ecc2121e..fef802b7af8c 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -11,6 +11,8 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MULTI_V4T=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_EP93XX=y CONFIG_MACH_ADSSPHERE=y CONFIG_MACH_EDB9301=y diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 15c68a646d51..aa502ab57404 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_EP93XX + bool "EP93xx-based" + depends on ARCH_MULTI_V4T + select ARCH_SPARSEMEM_ENABLE + select ARM_AMBA + select ARM_VIC + select CLKSRC_MMIO + select CPU_ARM920T + select GPIOLIB + help + This enables support for the Cirrus EP93xx series of CPUs. + if ARCH_EP93XX menu "Cirrus EP93xx Implementation Options" From 09f6b27d5ddd9ad0ec096d1b0f8decdacc70f0f8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 23 Feb 2014 11:30:13 +0100 Subject: [PATCH 0020/1268] ARM: dove: multiplatform support The dove platform is now ready to be enabled for multiplatform support, this patch does the switch over by modifying the Kconfig file, the defconfig and removing the last mach/*.h header that becomes obsolete with this. This work was originally done in 2015 as all the ARMv7 machiens gove moved over to multiplatform builds, but at the time it conflicted with some patches that Russell was trying to upstream, so we left it at that. I hope that there is no longer a need to keep dove separate from the rest, so we can either add it to the other ARMv7 platforms, or just replace it with the DT based platform code for the same hardware in mach-mvebu and remove mach-dove entirely. Acked-by: Andrew Lunn Cc: Russell King Cc: Jason Cooper Cc: Sebastian Hesselbarth Cc: Gregory Clement Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 14 -------- arch/arm/configs/dove_defconfig | 2 ++ arch/arm/mach-dove/Kconfig | 16 ++++++--- arch/arm/mach-dove/Makefile | 2 ++ arch/arm/mach-dove/include/mach/uncompress.h | 34 -------------------- 5 files changed, 16 insertions(+), 52 deletions(-) delete mode 100644 arch/arm/mach-dove/include/mach/uncompress.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2bd611beefe1..faf696173af7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -383,20 +383,6 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. -config ARCH_DOVE - bool "Marvell Dove" - select CPU_PJ4 - select GPIOLIB - select HAVE_PCI - select MVEBU_MBUS - select PINCTRL - select PINCTRL_DOVE - select PLAT_ORION_LEGACY - select SPARSE_IRQ - select PM_GENERIC_DOMAINS if PM - help - Support for the Marvell Dove SoC 88AP510 - config ARCH_PXA bool "PXA2xx/PXA3xx-based" select ARCH_MTD_XIP diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 33074fdab2ea..f8fb4758f80d 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -8,6 +8,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_DOVE=y CONFIG_MACH_DOVE_DB=y CONFIG_MACH_CM_A510=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 7747fe64420a..c30c69c664ea 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -1,7 +1,17 @@ # SPDX-License-Identifier: GPL-2.0 -if ARCH_DOVE +menuconfig ARCH_DOVE + bool "Marvell Dove" if ARCH_MULTI_V7 + select CPU_PJ4 + select GPIOLIB + select MVEBU_MBUS + select PINCTRL + select PINCTRL_DOVE + select PLAT_ORION_LEGACY + select PM_GENERIC_DOMAINS if PM + help + Support for the Marvell Dove SoC 88AP510 -menu "Marvell Dove Implementations" +if ARCH_DOVE config DOVE_LEGACY bool @@ -21,6 +31,4 @@ config MACH_CM_A510 Say 'Y' here if you want your kernel to support the CompuLab CM-A510 Board. -endmenu - endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index cdf163cab738..e83f6492834d 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include + obj-y += common.o obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h deleted file mode 100644 index ddf873f35e2b..000000000000 --- a/arch/arm/mach-dove/include/mach/uncompress.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define UART0_PHYS_BASE (0xf1000000 + 0x12000) - -#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) -#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) - -#define LSR_THRE 0x20 - -static inline void putc(const char c) -{ - int i; - - for (i = 0; i < 0x1000; i++) { - /* Transmit fifo not full? */ - if (*UART_LSR & LSR_THRE) - break; - } - - *UART_THR = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() From 2946aa908bb63539b566fc3ba0b867022787602b Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 18 Mar 2022 11:37:27 +0100 Subject: [PATCH 0021/1268] ARM: rockchip: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/20220318103729.157574-32-Julia.Lawall@inria.fr Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5ec58d004b7d..36915a073c23 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -137,7 +137,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) /* * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will - * stay at wfe state, once they are actived, they will check + * stay at wfe state, once they are activated, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc From 8eb5092e64de30c003d8fe16a7eeacbfe29b7b84 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 24 Feb 2022 12:58:43 +0000 Subject: [PATCH 0022/1268] arm64: dts: renesas: r9a07g054: Fillup the ADC stub node Fillup the ADC stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220224125843.29733-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 5d39e765c291..3ddf0f24071c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -260,8 +260,45 @@ }; adc: adc@10059000 { + compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G054_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G054_ADC_PRESETN>, + <&cpg R9A07G054_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; }; sbc: spi@10060000 { From ffe3f135dd28295114233d2a8073b3b15774b528 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:33 +0000 Subject: [PATCH 0023/1268] arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes Fillup the SDHI{0,1} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 26 ++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 3ddf0f24071c..0b0e924e28ae 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,13 +398,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; eth0: ethernet@11c20000 { From b0bb96e5162368814acdc76da7fdb2cd574f58c2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:34 +0000 Subject: [PATCH 0024/1268] arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins related to SDHI Drop deleting gpio-hog pins related to SDHI0/1 so that SDHI functionality gets enabled on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index fc334b4c2aa4..191ce17fbeac 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -20,7 +20,4 @@ &pinctrl { /delete-node/ can0-stb-hog; /delete-node/ can1-stb-hog; - /delete-node/ gpio-sd0-pwr-en-hog; - /delete-node/ sd0-dev-sel-hog; - /delete-node/ sd1-pwr-en-hog; }; From 791b7e1dcb9fe9f9e7f7dd1b6714cd8e0f6ee349 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:35 +0000 Subject: [PATCH 0025/1268] arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0b0e924e28ae..6e89bd126788 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -234,8 +234,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { From e3ab4573761418ba1b853ec33e5db723db279ff5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:36 +0000 Subject: [PATCH 0026/1268] arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodes Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 191ce17fbeac..4e07e1a0fb66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -16,8 +16,3 @@ model = "Renesas SMARC EVK based on r9a07g054l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; }; - -&pinctrl { - /delete-node/ can0-stb-hog; - /delete-node/ can1-stb-hog; -}; From 3f285c301cd788164fa776e1f95458c56e68a6ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 14:26:38 +0000 Subject: [PATCH 0027/1268] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220315142644.17660-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..c31eeb66319f 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -10,8 +10,8 @@ maintainers: - Geert Uytterhoeven description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,6 +20,7 @@ description: properties: compatible: enum: + - renesas,r9a07g043-sysc # RZ/G2UL - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L From 2f89bef90de4740be33b2cb4ba95e0107df0d25e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 14:26:39 +0000 Subject: [PATCH 0028/1268] soc: renesas: Identify RZ/G2UL SoC Add support for identifying the RZ/G2UL SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220315142644.17660-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 6 ++++++ drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fdc99a05a7e0..63477f05fbaf 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -296,6 +296,12 @@ config ARCH_R8A774B1 help This enables support for the Renesas RZ/G2N SoC. +config ARCH_R9A07G043 + bool "ARM64 Platform support for RZ/G2UL" + select ARCH_RZG2L + help + This enables support for the Renesas RZ/G2UL SoC variants. + config ARCH_R9A07G044 bool "ARM64 Platform support for RZ/G2L" select ARCH_RZG2L diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 92c7b42250ee..30192a099d38 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { .name = "RZ/G2L", }; +static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { + .name = "RZ/G2UL", +}; + static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; @@ -148,6 +152,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = { .id = 0x841c447, }; +static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { + .family = &fam_rzg2ul, + .id = 0x8450447, +}; + static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .family = &fam_rzv2l, .id = 0x8447447, @@ -340,6 +349,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A779F0 { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 }, #endif +#if defined(CONFIG_ARCH_R9A07G043) + { .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul }, +#endif #if defined(CONFIG_ARCH_R9A07G044) { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif @@ -378,6 +390,7 @@ static const struct renesas_id id_prr __initconst = { static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,bsid", .data = &id_bsid }, + { .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,prr", .data = &id_prr }, From e46a72e0398e570fbab5905ea6be67dc76d678f4 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:37 +0000 Subject: [PATCH 0029/1268] arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 73 +++++++++++++++++++++- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 6e89bd126788..fafb986fe3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -270,22 +270,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { From 8d3da65c4c40d77977799f58fa6465bdc723536f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:38 +0000 Subject: [PATCH 0030/1268] arm64: dts: renesas: r9a07g054: Fillup the sbc stub node Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index fafb986fe3bc..1207a99bf3fe 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,12 +398,20 @@ }; sbc: spi@10060000 { + compatible = "renesas,r9a07g054-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, + <&cpg CPG_MOD R9A07G054_SPI_CLK>; + resets = <&cpg R9A07G054_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { From f458b7707c9c4acabb7cdf6c0fcfde1a506b360f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:39 +0000 Subject: [PATCH 0031/1268] arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 24 +++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 1207a99bf3fe..50cb2f0e6e73 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -629,18 +629,36 @@ }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; + resets = <&cpg R9A07G054_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; + resets = <&cpg R9A07G054_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; + resets = <&cpg R9A07G054_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; }; From f35a868bcf95c066a00dcae9e7ee42d85eaf05b2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:40 +0000 Subject: [PATCH 0032/1268] arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes Fillup the WDT{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 50cb2f0e6e73..a3623e70f02c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -614,18 +614,48 @@ }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800C00 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { From cd0339ec25895c0be45656908442bc121bbadacb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:41 +0000 Subject: [PATCH 0033/1268] arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 80 +++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index a3623e70f02c..e3a9f78b7fb8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -96,9 +96,87 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { From a8e2a77b644ac23319f0e7c3e8d9dcd6dc9aebd1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:42 +0000 Subject: [PATCH 0034/1268] arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host support Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 74 ++++++++++++++++++++-- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e3a9f78b7fb8..7d9ea17352a4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -652,38 +652,98 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g054-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; + resets = <&cpg R9A07G054_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { From c9c4e5b7d202cce2f488a56c06332016380890b3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:43 +0000 Subject: [PATCH 0035/1268] arm64: dts: renesas: r9a07g054: Add USB2.0 device support Fillup the hsusb stub node in RZ/V2L (R9A07G054) SoC DTSI which enables USB2.0 device support. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 7d9ea17352a4..8bbdcf48bb61 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -747,8 +747,22 @@ }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g054", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { From 3f3c46d4e2cb38bfa7d1f24c2099a20229867d9d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:44 +0000 Subject: [PATCH 0036/1268] arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1 stub node Add SPI{0,2} nodes and fillup SPI1 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-13-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 47 ++++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 8bbdcf48bb61..9e730171efa8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -179,11 +179,52 @@ status = "disabled"; }; - spi1: spi@1004b000 { - reg = <0 0x1004b000 0 0x400>; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; + resets = <&cpg R9A07G054_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; + resets = <&cpg R9A07G054_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; + resets = <&cpg R9A07G054_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { From 1889f4798c443dfd4993ba9bbbf4ed7bf801d94b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 2 Mar 2022 07:40:43 +0000 Subject: [PATCH 0037/1268] arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0 Enable usb2.0 host/device functionality on RZ/G2LC SMARC EVK by deleting phyrst, usb2_phy{0,1}, ehci/ohci{0,1} and hsusb entries from board DT, so that entries from common dtsi kick in and make USB2.0 functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220302074043.21525-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 46 ------------------- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 11 +++++ 2 files changed, 11 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 5a5cea82a5d9..d5254b16b0b3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,24 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &i2c0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -50,22 +32,6 @@ status = "disabled"; }; -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -77,15 +43,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 37ff2091582e..5f5ec21e655c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -90,5 +90,16 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUS */ + ; /* OVC */ + }; }; From a2b642d89e4beeddbfbd7be6108db2b7aaef78b6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:52 +0000 Subject: [PATCH 0038/1268] arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes Sort the pinctrl nodes alphabetically. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 5f5ec21e655c..53759c3ddecb 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -12,11 +12,6 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - pinmux = , /* TxD */ - ; /* RxD */ - }; - #if SW_SCIF_CAN /* SW8 should be at position 2->1 */ can1_pins: can1 { @@ -25,13 +20,6 @@ }; #endif - scif1_pins: scif1 { - pinmux = , /* TxD */ - , /* RxD */ - , /* CTS# */ - ; /* RTS# */ - }; - #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ can1-stb-hog { @@ -47,6 +35,18 @@ }; #endif + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; From 0a7c1c888a0c0276837f2cd7190683474a136506 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:53 +0000 Subject: [PATCH 0039/1268] arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi On RZ/G2L SoM module, the Audio codec is connected to i2c3 bus whereas on RZ/G2LC, it is connected to i2c2 bus. So move out i2c3 and wm8978 nodes from common dtsi to soc specific dtsi. While at it add wm8978 node to RZ/G2LC SoC specific dtsi to fix the build error. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 15 --------------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index d5254b16b0b3..dc39b05e9256 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -26,12 +26,6 @@ status = "disabled"; }; -&i2c3 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 588117aafaca..8dd1c69a6749 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -26,7 +26,6 @@ serial0 = &scif0; i2c0 = &i2c0; i2c1 = &i2c1; - i2c3 = &i2c3; }; chosen { @@ -131,20 +130,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 33ddfd18bd56..c934cd3633a4 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -14,6 +14,21 @@ / { aliases { serial1 = &scif2; + i2c3 = &i2c3; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index df7631fe5fac..55d3b73f84e7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -43,6 +43,7 @@ / { aliases { serial1 = &scif1; + i2c2 = &i2c2; }; }; @@ -59,6 +60,16 @@ }; #endif +&i2c2 { + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated From 4fa1edc83b2b2b467ed47bd682c7beab81a38ef5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:54 +0000 Subject: [PATCH 0040/1268] arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2} Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ------------ .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 6 +++++- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index dc39b05e9256..52b834205126 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,18 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 53759c3ddecb..1322e5bcd456 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -35,6 +35,21 @@ }; #endif + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 55d3b73f84e7..f73b4acb8f9e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -61,7 +61,11 @@ #endif &i2c2 { - status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; wm8978: codec@1a { compatible = "wlf,wm8978"; From 4eb6a6bb8ef31491c217167ecce2c0a26fd4f34e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:55 +0000 Subject: [PATCH 0041/1268] arm64: dts: renesas: rzg2lc-smarc: Enable Audio Enable Audio on RZ/G2LC SMARC EVK by deleting ssi0 entries from board DT and adding pincontrol entries to the soc-pinctrl dtsi, so that entries from common dtsi kick in and make audio functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 52b834205126..74a2f2bade10 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -19,9 +19,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 1322e5bcd456..d275a55333e3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -106,6 +106,13 @@ input-enable; }; + ssi0_pins: ssi0 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; + usb0_pins: usb0 { pinmux = , /* VBUS */ , /* OVC */ From 018d7b93477fbb04ba7b4bc4c355793d644e45da Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:33 +0000 Subject: [PATCH 0042/1268] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 88a7938017aa..80c9a1146cb7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -110,6 +110,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -175,6 +187,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; From a081c4fe98f6662fbddb1597a6203be669641af1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:34 +0000 Subject: [PATCH 0043/1268] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 80c9a1146cb7..05b117ac414c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -84,6 +84,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ From 6f57895c49bc36a6ba125b9926d4b9699376e656 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:35 +0000 Subject: [PATCH 0044/1268] arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator Add vdd core regulator (1.1 V) for GPU. This patch add regulator support for GPU. The H/W manual mentions nothing about a GPU regulator. So using vdd core regulator for GPU. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 05b117ac414c..959a0ad1d367 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -41,6 +41,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -84,6 +93,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; }; From 809823b853a2559d04948ea43800408f00c8db23 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:22 +0000 Subject: [PATCH 0045/1268] arm64: dts: renesas: r9a07g054: Fillup the GPU node Renesas RZ/V2L SoC has Mali-G31 GPU, this patch fills up the GPU node and adds opp table to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 62 +++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 9e730171efa8..e4f1defa0ff8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -83,6 +83,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -606,8 +650,24 @@ }; gpu: gpu@11840000 { + compatible = "renesas,r9a07g054-mali", + "arm,mali-bifrost"; reg = <0x0 0x11840000 0x0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPU_RESETN>, + <&cpg R9A07G054_GPU_AXI_RESETN>, + <&cpg R9A07G054_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@11900000 { From 4b7e7f10835a504501a04a82498234da78c4117e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:23 +0000 Subject: [PATCH 0046/1268] arm64: dts: renesas: r9a07g054: Add OPP table Add OPP table for RZ/V2L SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e4f1defa0ff8..bdf0a104e82c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +92,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -74,6 +102,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From f6a2f28ab19ca5ce5bbd3a821fe19468d7c921dc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:24 +0000 Subject: [PATCH 0047/1268] arm64: dts: renesas: r9a07g054: Add TSU node Add TSU and thermal-zones nodes to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index bdf0a104e82c..f35aa0311e9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -589,6 +589,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g054-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; + resets = <&cpg R9A07G054_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g054-rpc-if", "renesas,rzg2l-rpc-if"; @@ -974,6 +984,37 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, From 9a4259e59694136add708608fce861a1beff9635 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 9 Mar 2022 19:06:31 +0000 Subject: [PATCH 0048/1268] arm64: dts: renesas: falcon-cpu: Use INTC_EX for SN65DSI86 The INTC block is a better choice for handling the interrupts on the V3U as the INTC will always be powered, while the GPIO block may be de-clocked if not in use. Further more, it may be likely to have a lower power consumption as it does not need to drive the pins. Switch the interrupt parent and interrupts definition from gpio1 to irq0 on intc_ex, and configure the PFC accordingly. Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20220309190631.1576372-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 6af3f4f4f268..53c4a26198e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -192,14 +192,17 @@ clock-frequency = <400000>; bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + compatible = "ti,sn65dsi86"; reg = <0x2c>; clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; vccio-supply = <®_1p8v>; vpll-supply = <®_1p8v>; @@ -271,6 +274,11 @@ function = "i2c6"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_6_18", "GP_6_19", "GP_6_20"; bias-pull-up; From d63833b8699c585d9ed32d968563b5eba69df9f6 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:07 +0100 Subject: [PATCH 0049/1268] arm64: dts: renesas: r8a779a0: Add CANFD device node This patch adds a CANFD device node for r8a779a0. Based on patch by Kazuya Mizuguchi. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c4be288b1912..c80f4584035e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -24,6 +24,13 @@ i2c6 = &i2c6; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -596,6 +603,55 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779a0-canfd"; + reg = <0 0xe6660000 0 0x8000>; + interrupts = , + ; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779A0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen3"; From d2194187aa4f9a4c2df010962e4e008efc3f930b Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:08 +0100 Subject: [PATCH 0050/1268] arm64: dts: renesas: falcon: Enable CANFD 0 and 1 Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index e46dc9aa0a43..b2e67b82caf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -37,6 +37,20 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &i2c0 { eeprom@51 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -65,4 +79,14 @@ }; }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; }; From 0182581a9f63764bcbdbc68e98881b50e03fc4c4 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Sat, 19 Mar 2022 23:33:05 +0100 Subject: [PATCH 0051/1268] arm64: dts: renesas: r8a77961: Add CAN-FD node Add the device node for the CAN-FD device on R-Car M3-W+. Signed-off-by: Koji Matsuoka Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220319223306.60782-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 68cbbb322acf..7d522ea5fca2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1222,6 +1222,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77961-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77961_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; From ca9df4a75a208f3294a9a09b84ffa1bc89d3e0df Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 14:00:33 +0000 Subject: [PATCH 0052/1268] arm64: defconfig: Enable ARCH_R9A07G054 Enable support for the Renesas RZ/V2L SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308140033.10501-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 50aa3d75ab4f..2836f3c5d361 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1097,6 +1097,7 @@ CONFIG_ARCH_R8A774E1=y CONFIG_ARCH_R8A774A1=y CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R9A07G044=y +CONFIG_ARCH_R9A07G054=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y From 33c7874b44324fe9657d19ca01ef4ae4403a5a4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Tue, 1 Mar 2022 15:31:47 -0500 Subject: [PATCH 0053/1268] arm64: dts: mediatek: Format mediatek,larbs as an array of phandles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas") updated the mediatek,larbs property in the mediatek,iommu.yaml dt-binding to make it clearer that the phandles passed to the property are independent, rather than subsequent arguments to the first phandle. Update the mediatek,larbs property in the arm64 Devicetrees to use the same formatting. This change doesn't impact any behavior: the compiled dtb is exactly the same. It does however fix the warnings generated by dtbs_check. Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index a27b7628c5f7..86579330a8bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,8 +329,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb6>; #iommu-cells = <1>; }; @@ -346,7 +346,7 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; + mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9029051624a6..54655f2feb04 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -174,7 +174,7 @@ iommu: m4u@10203000 { compatible = "mediatek,mt8167-m4u"; reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0 &larb1 &larb2>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; interrupts = ; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 2b7d331a4588..042feaedda4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -588,8 +588,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4b08691ed39e..5d4a1dd55adc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -682,8 +682,8 @@ compatible = "mediatek,mt8183-m4u"; reg = <0 0x10205000 0 0x1000>; interrupts = ; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 - &larb4 &larb5 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; #iommu-cells = <1>; }; From 261691b40128e6b76bb94d562457d8a5236cc7fa Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:13 +0800 Subject: [PATCH 0054/1268] arm64: dts: mt8192: Add pwrap node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..76428599444e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names = "clk13m"; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; From c63556ec6bfe21cde6ab2fb0b651112bc5e99e56 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:16 +0800 Subject: [PATCH 0055/1268] arm64: dts: mt8192: Add SCP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 76428599444e..4f26a398d970 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -679,6 +679,18 @@ status = "disabled"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8192-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names = "sram", "l1tcm", "cfg"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From 40de66b8bbbb6137022652954167d5c570bb93c2 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:17 +0800 Subject: [PATCH 0056/1268] arm64: dts: mt8192: Add usb-phy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 4f26a398d970..946ebcb2bb5f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -848,6 +848,28 @@ #clock-cells = <1>; }; + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11e40000 0x1000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, From e5aac2258e666cdfe7e027766b89af639cd5fb08 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:18 +0800 Subject: [PATCH 0057/1268] arm64: dts: mt8192: Add xhci node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 946ebcb2bb5f..be82e0766129 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -691,6 +692,29 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "host"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x420 102>; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From 27f0eb16b0d417c155e96b5d3b89074699944e09 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:22 +0800 Subject: [PATCH 0058/1268] arm64: dts: mt8192: Fix nor_flash status disable typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct nor_flash status disable typo of mt8192 SoC. Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-11-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index be82e0766129..a3721f442138 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -727,7 +727,7 @@ assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; audsys: clock-controller@11210000 { From 4d50a433d0fde2c610628a7b40a0291899861482 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:23 +0800 Subject: [PATCH 0059/1268] arm64: dts: mt8192: Add efuse node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add efuse node for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-12-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a3721f442138..3d51e1ef7a6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -736,6 +736,21 @@ #clock-cells = <1>; }; + efuse: efuse@11c10000 { + compatible = "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_e_data1: data1@1c0 { + reg = <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x68>; + }; + }; + i2c3: i2c@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, From 4a65b0f1bec51872b406a8f74a66c0e6e298423c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:26 +0800 Subject: [PATCH 0060/1268] arm64: dts: mt8192: Add m4u and smi nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-15-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 3d51e1ef7a6f..579abbf4488e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -967,24 +968,114 @@ #clock-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8192-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible = "mediatek,mt8192-m4u"; + reg = <0 0x1401d000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb4>, <&larb5>, <&larb7>, + <&larb9>, <&larb11>, <&larb13>, + <&larb14>, <&larb16>, <&larb17>, + <&larb18>, <&larb19>, <&larb20>; + interrupts = ; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells = <1>; + }; + imgsys: clock-controller@15020000 { compatible = "mediatek,mt8192-imgsys"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@1502e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8192-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: larb@1582e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1600d000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible = "mediatek,mt8192-vdecsys_soc"; reg = <0 0x1600f000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@1602e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8192-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -997,12 +1088,78 @@ #clock-cells = <1>; }; + larb7: larb@17010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@1a001000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a011000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8192-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -1027,10 +1184,43 @@ #clock-cells = <1>; }; + larb20: larb@1b00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b00f000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b10f000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible = "mediatek,mt8192-mdpsys"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; + + larb2: larb@1f002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1f002000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + clocks = <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; From 19c66219e4d5b813ebbd28621cfe9c450659ded7 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:31 +0800 Subject: [PATCH 0061/1268] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220318144534.17996-20-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- include/dt-bindings/reset/mt8192-resets.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..764ca9910fa9 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -27,4 +27,7 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* MMSYS resets */ +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From 7663f7a26b335a53102a0893824689182ac64e42 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 16 Feb 2022 19:31:29 +0800 Subject: [PATCH 0062/1268] dt-bindings: arm: mediatek: Add mt8195 pericfg compatible Add mt8195 pericfg compatible to binding document. Signed-off-by: Tinghan Shen Acked-by: Rob Herring Acked-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220216113131.13145-2-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe34bab..611f666f359d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon - items: From b2edd51979d2861e75a9b20ac0e566e9a0770d81 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:29 +0800 Subject: [PATCH 0063/1268] arm64: dts: mt8192: Add dpi node Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-18-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 579abbf4488e..c6439a010e06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -999,6 +999,17 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + iommu0: m4u@1401d000 { compatible = "mediatek,mt8192-m4u"; reg = <0 0x1401d000 0 0x1000>; From e530d080932d0db52071c9bec20d60b4a3d9035c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:13 +0800 Subject: [PATCH 0064/1268] arm64: dts: mt8192: Add PCIe node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220330133816.30806-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c6439a010e06..0d32df382f10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -716,6 +716,41 @@ status = "disabled"; }; + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0 0x11230000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, + <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "top_133m"; + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From aa8f3711fc87f7d9b8edee6f09e44b3f9113f081 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:15 +0800 Subject: [PATCH 0065/1268] arm64: dts: mt8192: Add H264 venc device node Adds H264 venc node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220330133816.30806-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 0d32df382f10..a6da7b04b9d4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1145,6 +1145,29 @@ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; }; + vcodec_enc: vcodec@17020000 { + compatible = "mediatek,mt8192-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts = ; + mediatek,scp = <&scp>; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc-set1"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; From 9d7370a56d1871e924377872985a13f6cd104e82 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Mar 2022 10:19:32 +0100 Subject: [PATCH 0066/1268] soc: mediatek: mmsys: Add sw0_rst_offset for MT8192 MT8192 has the same sw0 reset offset as MT8186: add the parameter to be able to use mmsys as a reset controller for managing at least the DSI reset line. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Link: https://lore.kernel.org/r/20220323091932.10648-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 4fc4c2c9ea20..893cec3c9651 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -70,6 +70,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { From c1ed0f41032f54e47c03088f096f8b37cae40d8e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:23 +0100 Subject: [PATCH 0067/1268] ARM: dts: exynos: fix ethernet node name for different odroid boards The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20220216074927.3619425-6-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index efaf7533e84f..5ddbb6cbe1bf 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -119,7 +119,7 @@ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; - ethernet: usbether@2 { + ethernet: ethernet@2 { compatible = "usb0424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index a9fada51eb50..eb063f24b2bb 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -81,7 +81,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index e54a3391854d..c1715123bea0 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -655,7 +655,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@2 { + ethernet: ethernet@2 { compatible = "usb0424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 62c5928aa994..749f051ffe70 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -118,7 +118,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cecaeb69e623..8cf3d644a4c1 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -85,7 +85,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ From 2e33a7b5fdb3930a9b1051bc792dbdc6a7490aae Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:24 +0100 Subject: [PATCH 0068/1268] ARM: dts: exynos: fix compatible strings for Ethernet USB devices Fix compatible string for Ethernet USB device as required by USB device schema: Documentation/devicetree/bindings/usb/usb-device.yaml The textual representation of VID and PID shall be in lower case hexadecimal with leading zeroes suppressed. Since there are no kernel driver matching against this compatibles, I expect no regressions with this patch. At the same time, without this fix, we are not be able to validate this device nodes with newly provided DT schema. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20220216074927.3619425-7-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 6 +++--- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 5ddbb6cbe1bf..36c369c42b77 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -120,7 +120,7 @@ phy-names = "hsic0", "hsic1"; ethernet: ethernet@2 { - compatible = "usb0424,9730"; + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index eb063f24b2bb..1f17cc30ed14 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -70,19 +70,19 @@ phy-names = "hsic0"; hub@2 { - compatible = "usb0424,3503"; + compatible = "usb424,3503"; reg = <2>; #address-cells = <1>; #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index c1715123bea0..d1cbc6b8a570 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -656,7 +656,7 @@ #size-cells = <0>; ethernet: ethernet@2 { - compatible = "usb0424,9730"; + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 749f051ffe70..e3154a1cae23 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -113,13 +113,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 8cf3d644a4c1..a378d4937ff7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -80,13 +80,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; From a0861079a218aeca314eba38245a47f33d51f476 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 28 Mar 2022 10:26:38 +0200 Subject: [PATCH 0069/1268] ARM: s3c: Drop config symbol S3C24XX_PWM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only effect of this symbol is to select PWM_SAMSUNG. Drop it and fix the affected defconfigs to still keep PWM_SAMSUNG=y. Developers using MACH_NEO1973_GTA02 and/or MACH_RX1950 now have to manually select PWM and PWM_SAMSUNG (and get the freedom to select is as a module or not at all). A side effect of this change is that allmodconfig now contains PWM_SAMSUNG=m (which was =y before). Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20220328082638.112185-1-u.kleine-koenig@pengutronix.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/mini2440_defconfig | 3 ++- arch/arm/configs/s3c2410_defconfig | 2 ++ arch/arm/mach-s3c/Kconfig | 8 -------- arch/arm/mach-s3c/Kconfig.s3c24xx | 2 -- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 898490aaa39e..c7741289f213 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -6,7 +6,6 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_COMPAT_BRK is not set CONFIG_ARCH_S3C24XX=y CONFIG_S3C_ADC=y -CONFIG_S3C24XX_PWM=y # CONFIG_CPU_S3C2410 is not set CONFIG_CPU_S3C2440=y CONFIG_MACH_MINI2440=y @@ -228,6 +227,8 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_S3C24XX_DMAC=y +CONFIG_PWM=y +CONFIG_PWM_SAMSUNG=y CONFIG_EXT2_FS=m CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 153009130dab..0ec00aec2e8a 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -358,6 +358,8 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y CONFIG_S3C24XX_DMAC=y +CONFIG_PWM=y +CONFIG_PWM_SAMSUNG=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/mach-s3c/Kconfig b/arch/arm/mach-s3c/Kconfig index 1899fc3f44fd..54548c051402 100644 --- a/arch/arm/mach-s3c/Kconfig +++ b/arch/arm/mach-s3c/Kconfig @@ -207,14 +207,6 @@ config SAMSUNG_DEV_PWM help Compile in platform device definition for PWM Timer -config S3C24XX_PWM - bool "PWM device support" - select PWM - select PWM_SAMSUNG - help - Support for exporting the PWM timer blocks via the pwm device - system - config GPIO_SAMSUNG def_bool y diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx index 000e3e234f71..ee4b79ac3755 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c24xx +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -532,7 +532,6 @@ config MACH_NEO1973_GTA02 select MFD_PCF50633 select PCF50633_GPIO select POWER_SUPPLY - select S3C24XX_PWM select S3C_DEV_USB_HOST help Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone @@ -544,7 +543,6 @@ config MACH_RX1950 select S3C2410_COMMON_DCLK select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_16934400 - select S3C24XX_PWM select S3C_DEV_NAND help Say Y here if you're using HP iPAQ rx1950 From 56653827f0d7bc7c2d8bac0e119fd1521fa9990a Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 20 Mar 2022 08:10:30 +0100 Subject: [PATCH 0070/1268] memory: samsung: exynos5422-dmc: Avoid some over memory allocation 'dmc->counter' is a 'struct devfreq_event_dev **', so there is some over memory allocation. 'counters_size' should be computed with 'sizeof(struct devfreq_event_dev *)'. Use 'sizeof(*dmc->counter)' instead to fix it. While at it, use devm_kcalloc() instead of devm_kzalloc()+open coded multiplication. Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/69d7e69346986e2fdb994d4382954c932f9f0993.1647760213.git.christophe.jaillet@wanadoo.fr Signed-off-by: Krzysztof Kozlowski --- drivers/memory/samsung/exynos5422-dmc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 9c8318923ed0..4733e7898ffe 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -1322,7 +1322,6 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) */ static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) { - int counters_size; int ret, i; dmc->num_counters = devfreq_event_get_edev_count(dmc->dev, @@ -1332,8 +1331,8 @@ static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) return dmc->num_counters; } - counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; - dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + dmc->counter = devm_kcalloc(dmc->dev, dmc->num_counters, + sizeof(*dmc->counter), GFP_KERNEL); if (!dmc->counter) return -ENOMEM; From c3d3727c8531ba78fc725995ce34cf948ebf1dae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:46:08 +0200 Subject: [PATCH 0071/1268] ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on Odroid Passing maximum frequency of LPDDR3 memory timings as unit address was deprecated in favor of 'max-freq' property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20220206135918.211990-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2f65dcf6ba73..35818c4cd852 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,6 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; @@ -358,10 +356,9 @@ tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings { compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; From aa8ea8cc95dec8bc7370773271e133c1b3cc864a Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:22 +0100 Subject: [PATCH 0072/1268] ARM: dts: bcm283x: fix ethernet node name It should be "ethernet@x" instead of "usbether@x" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi | 2 +- arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi index 967e081cb9c2..882b13807075 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi index dc7ae776db5f..4273b90b53cc 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi @@ -11,7 +11,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; From f4324583cd4d4979ff2e885a44b8335eb4c4bfa3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:47:40 +0200 Subject: [PATCH 0073/1268] arm64: dts: exynos: move aliases to board in Exynos850 The aliases for typical blocks which are disabled by default in DTSI (like I2C, UART and MMC) should be defined in the board DTS. The board should add aliases only for enabled blocks according to its specific order. On Exynos850, move aliases of enabled blocks to E850-96 board and remove unused ones. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220221075219.10827-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 5 +++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 16 ---------------- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7b5a61d22cc5..f52a55f644f7 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -20,6 +20,11 @@ model = "WinLink E850-96 board"; compatible = "winlink,e850-96", "samsung,exynos850"; + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + chosen { stdout-path = &serial_0; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..1c6d8fdf453c 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -29,22 +29,6 @@ pinctrl3 = &pinctrl_hsi; pinctrl4 = &pinctrl_core; pinctrl5 = &pinctrl_peri; - mmc0 = &mmc_0; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &hsi2c_0; - i2c8 = &hsi2c_1; - i2c9 = &hsi2c_2; - i2c10 = &hsi2c_3; - i2c11 = &hsi2c_4; }; arm-pmu { From cca50a59f60a6b2b5aa2c90d8c173da89f567ee3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:51:20 +0200 Subject: [PATCH 0074/1268] ARM: dts: exynos: add a specific compatible to MCT One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos3250 and all Exynos5 SoCs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos3250.dtsi | 3 ++- arch/arm/boot/dts/exynos5250.dtsi | 3 ++- arch/arm/boot/dts/exynos5260.dtsi | 3 ++- arch/arm/boot/dts/exynos54xx.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index ae644315855d..41bb421e67c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = , , diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5baaa7eb71a4..63d1dcf2c55c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 56271e7c4587..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -333,7 +333,8 @@ }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0xb00>; interrupts-extended = <&combiner 23 3>, <&combiner 23 4>, From 2616922241706ec5c2c5ae95d5ac1d3120575ded Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:52:55 +0200 Subject: [PATCH 0075/1268] arm64: dts: exynos: add a specific compatible to MCT One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos5433 and Exynos850. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-4-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos850.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = , , diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 1c6d8fdf453c..9076afd4bb3e 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -165,7 +165,8 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = , , From 22cbcb8f4a17c194d208f686fc3ea37fc860bd71 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:53:08 +0200 Subject: [PATCH 0076/1268] arm64: dts: tesla: add a specific compatible to MCT on FSD One compatible is used for the Multi-Core Timer on Tesla FSD SoC, which is correct but not specific enough. The MCT blocks have different number of interrupts, so add a second specific compatible to Tesla FSD. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-5-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 9a652abcbcac..10c217a57a7d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -727,7 +727,7 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = , , From 04398e04173f1be0b21d7cd50c54e8affcebe106 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:54:46 +0200 Subject: [PATCH 0077/1268] ARM: dts: exynos: drop deprecated SFR region from MIPI phy Commit e4b3d38088df ("phy: exynos-video-mipi: Fix regression by adding support for PMU regmap") deprecated the usage of unit address in MIPI phy node, in favor of a syscon phandle. Deprecating was a correct approach because that unit address was actually coming from Power Management Unit SFR range so its usage here caused overlapped memory mapping. In 2016 commit 26dbadba495f ("phy: exynos-mipi-video: Drop support for direct access to PMU") fully removed support for parsing that MIPI phy unit address (SFR range) but the address stayed in Exynos5250 DTSI for compatibility reasons. Remove that deprecated unit address from Exynos5250 MIPI phy, because it has been almost 6 years since it was deprecated and it causes now DT schema validation warnings: video-phy@10040710: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Any out-of-tree users of Exynos5250 DTSI, should update their code to use newer syscon property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314184113.251013-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5250.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 63d1dcf2c55c..df80ddfada2d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -818,15 +818,14 @@ status = "disabled"; }; - dp_phy: video-phy { + dp_phy: video-phy-0 { compatible = "samsung,exynos5250-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; - mipi_phy: video-phy@10040710 { + mipi_phy: video-phy-1 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040710 0x100>; #phy-cells = <1>; syscon = <&pmu_system_controller>; }; From b412be7d3c0a248db0de4b7b53ee6ad44d49c71b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:55:19 +0200 Subject: [PATCH 0078/1268] ARM: dts: exynos: align EHCI/OHCI nodes with dtschema on Exynos4 The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314181948.246434-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e81b3ee4e0f7..5fd17bc52321 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -373,7 +373,7 @@ status = "disabled"; }; - ehci: ehci@12580000 { + ehci: usb@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = ; @@ -384,7 +384,7 @@ phy-names = "host", "hsic0", "hsic1"; }; - ohci: ohci@12590000 { + ohci: usb@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = ; From ab92681ca16194c966844ed4dd2c336705e0c727 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:55:46 +0200 Subject: [PATCH 0079/1268] ARM: dts: s5pv210: align EHCI/OHCI nodes with dtschema The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314181948.246434-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/s5pv210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 353ba7b09a0c..a7aca54832d9 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -427,7 +427,7 @@ status = "disabled"; }; - ehci: ehci@ec200000 { + ehci: usb@ec200000 { compatible = "samsung,exynos4210-ehci"; reg = <0xec200000 0x100>; interrupts = <23>; @@ -444,7 +444,7 @@ }; }; - ohci: ohci@ec300000 { + ohci: usb@ec300000 { compatible = "samsung,exynos4210-ohci"; reg = <0xec300000 0x100>; interrupts = <23>; From 061d09499fd1fcf793291009d9a21899c4fb871f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:56:11 +0200 Subject: [PATCH 0080/1268] ARM: dts: s5pv210: Use standard arrays of generic PHYs for EHCI/OHCI device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move USB PHYs to a standard arrays for S5PV210 EHCI/OHCI devices. This resolves the conflict between S5PV210 EHCI/OHCI sub-nodes and generic USB device bindings. Suggested-by: Måns Rullgård Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220314181948.246434-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/s5pv210.dtsi | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index a7aca54832d9..4ea1e638432a 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -434,14 +434,9 @@ interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; ohci: usb@ec300000 { @@ -451,14 +446,9 @@ interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; mfc: codec@f1700000 { From 170a0c56c5ec597fa15447e63272827a80a19be1 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 18 Mar 2022 11:37:26 +0100 Subject: [PATCH 0081/1268] ARM: s3c: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/20220318103729.157574-31-Julia.Lawall@inria.fr Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/iotiming-s3c2410.c | 2 +- arch/arm/mach-s3c/pm-s3c64xx.c | 2 +- arch/arm/mach-s3c/s3c24xx.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-s3c/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c index 28d9f473e24a..09f388d8f824 100644 --- a/arch/arm/mach-s3c/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c/iotiming-s3c2410.c @@ -259,7 +259,7 @@ static const unsigned int tacc_tab[] = { /** * get_tacc - turn tACC value into cycle time * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @val: The bank timing register value, shifed down. + * @val: The bank timing register value, shifted down. */ static unsigned int get_tacc(unsigned long hclk_tns, unsigned long val) diff --git a/arch/arm/mach-s3c/pm-s3c64xx.c b/arch/arm/mach-s3c/pm-s3c64xx.c index 4f1778123dee..2529f21736ff 100644 --- a/arch/arm/mach-s3c/pm-s3c64xx.c +++ b/arch/arm/mach-s3c/pm-s3c64xx.c @@ -323,7 +323,7 @@ void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) /* S3C64XX UART blocks only support level interrupts, so ensure that * when we restore unused UART blocks we force the level interrupt - * settigs. */ + * settings. */ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; /* We have a constraint on changing the clock type of the UART diff --git a/arch/arm/mach-s3c/s3c24xx.c b/arch/arm/mach-s3c/s3c24xx.c index ccfed48c98aa..37eaf9480da7 100644 --- a/arch/arm/mach-s3c/s3c24xx.c +++ b/arch/arm/mach-s3c/s3c24xx.c @@ -146,7 +146,7 @@ static struct map_desc s3c_iodesc[] __initdata __maybe_unused = { IODESC_ENT(UART) }; -/* read cpu identificaiton code */ +/* read cpu identification code */ static unsigned long s3c24xx_read_idcode_v5(void) { From 05e3a8cb079b965e4a0759551770bc507dcfa90f Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 18 Mar 2022 11:37:08 +0100 Subject: [PATCH 0082/1268] ARM: mm: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Signed-off-by: Florian Fainelli --- arch/arm/mm/cache-b15-rac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index bdc07030997b..9c1172f26885 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -74,7 +74,7 @@ static inline void __b15_rac_flush(void) __raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset); do { /* This dmb() is required to force the Bus Interface Unit - * to clean oustanding writes, and forces an idle cycle + * to clean outstanding writes, and forces an idle cycle * to be inserted. */ dmb(); From a14a56a3dd6bb45aa7c0ef1a665839656f2bcce3 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 11 Mar 2022 14:11:14 +0530 Subject: [PATCH 0083/1268] ARM: dts: bcm-cygnus: Update spi clock properties PL022 binding require two clocks to be defined but broadcom cygnus platform doesn't comply with bindings and define only one clock. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Florian Fainelli Signed-off-by: Kuldeep Singh Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ad65be871938..f9f79ed82518 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -397,8 +397,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -409,8 +409,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -421,8 +421,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; From 0a5ccc9109fa08f2dd6179490f24005e02ee2356 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 18 Mar 2022 11:37:29 +0100 Subject: [PATCH 0084/1268] ARM: brcmstb: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Signed-off-by: Florian Fainelli --- arch/arm/mach-bcm/platsmp-brcmstb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c index 4555f21e7077..9b457714a41c 100644 --- a/arch/arm/mach-bcm/platsmp-brcmstb.c +++ b/arch/arm/mach-bcm/platsmp-brcmstb.c @@ -59,7 +59,7 @@ static u32 hif_cont_reg; /* * We must quiesce a dying CPU before it can be killed by the boot CPU. Because * one or more cache may be disabled, we must flush to ensure coherency. We - * cannot use traditionl completion structures or spinlocks as they rely on + * cannot use traditional completion structures or spinlocks as they rely on * coherency. */ static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state); From 130b5e32ba9d2d2313e39cf3f6d0729bff02b76a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 30 Mar 2022 14:05:27 +0200 Subject: [PATCH 0085/1268] ARM: dts: BCM5301X: Update pin controller node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: cru-bus@100: 'pin-controller@1c0' does not match any of the regexes: '^clock-controller@[a-f0-9]+$', '^phy@[a-f0-9]+$', '^pinctrl@[a-f0-9]+$', '^syscon@[a-f0-9]+$', '^thermal@[a-f0-9]+$' From schema: Documentation/devicetree/bindings/mfd/brcm,cru.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pin-controller@1c0: $nodename:0: 'pin-controller@1c0' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' From schema: Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml Ref: e7391b021e3f ("dt-bindings: mfd: brcm,cru: Rename pinctrl node") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 603c700c706f..65f8a759f1e3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -455,7 +455,7 @@ reg = <0x180 0x4>; }; - pinctrl: pin-controller@1c0 { + pinctrl: pinctrl@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; From 90103611d573c5c238350f9b1d7cb682c62f5681 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:19:58 +0300 Subject: [PATCH 0086/1268] ARM: dts: BCM5301X: Fix DTC warning for NAND node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells and #size-cells properties on the nand@0 node to fix the warning below. Warning (avoid_unnecessary_addr_size): /nand-controller@18028000/nand@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index be9a00ff752d..bdf1b4a608e6 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -10,8 +10,6 @@ nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "brcm,bcm947xx-cfe-partitions"; From e5ff0a7aab3ef5dd8ec7636b936c95179aa5ddfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:19:59 +0300 Subject: [PATCH 0087/1268] ARM: dts: BCM5301X: Remove cell properties from srab ports on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove #address-cells and #size-cells properties from the ports node of &srab. They are already defined on bcm5301x.dtsi, there's no need to define them again. Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 82f9629f0abb..cf793c558437 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright (C) 2021 Arınç ÜNAL + * Copyright (C) 2021-2022 Arınç ÜNAL */ /dts-v1/; @@ -177,9 +177,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; From 4b7a67420a34ebd8fbf0111221a8bfd8001d418d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:20:00 +0300 Subject: [PATCH 0088/1268] ARM: dts: BCM5301X: Add rgmii to port@5 of Broadcom switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define phy-mode of the Broadcom switch's port@5 as rgmii. This doesn't seem to matter but let's explicitly define it since phy-mode as rgmii is defined on the other side which is port@6 of the Realtek switch. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index cf793c558437..5696dd5fbaf4 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -205,6 +205,7 @@ sw0_p5: port@5 { reg = <5>; label = "extsw"; + phy-mode = "rgmii"; fixed-link { speed = <1000>; From 7f7f8c7b9f3cbae1355fb3b0ce4ea9d6f1552521 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:20:01 +0300 Subject: [PATCH 0089/1268] ARM: dts: BCM5301X: Retrieve gmac1 MAC address from NVRAM on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The et1macaddr NVRAM variable contains a MAC address for gmac1 on Asus RT-AC88U. Add NVMEM cell for it and reference it in the gmac1 node. Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 5696dd5fbaf4..2f944d1c0330 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -25,6 +25,9 @@ nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + }; }; leds { @@ -239,6 +242,11 @@ }; }; +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; From e403fff3b848107e2da92b9a567a926aa5943f7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:19 +0300 Subject: [PATCH 0090/1268] dt-bindings: arm: bcm: fix BCM53012 and BCM53016 SoC strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix inaccurate SoC strings brcm,brcm53012 and brcm,brcm53016 to respectively brcm,bcm53012 and brcm,bcm53016. Fixes: 4cb5201fcb5d ("dt-bindings: arm: bcm: Convert BCM4708 to YAML") Fixes: a2e385f5374d ("dt-bindings: ARM: add bindings for the Meraki MR32") Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 434d3c6db61e..f0e2a20d22d5 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -84,8 +84,8 @@ properties: - brcm,bcm953012hr - brcm,bcm953012k - meraki,mr32 - - const: brcm,brcm53012 - - const: brcm,brcm53016 + - const: brcm,bcm53012 + - const: brcm,bcm53016 - const: brcm,bcm4708 additionalProperties: true From ca41a8b302601b2547ea8aac4306efd8356d85a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:20 +0300 Subject: [PATCH 0091/1268] dt-bindings: arm: bcm: create new description for BCM53016 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a new description for BCM53016 and move Meraki MR32 under it. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index f0e2a20d22d5..8a97ee048053 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -83,8 +83,13 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k - - meraki,mr32 - const: brcm,bcm53012 + - const: brcm,bcm4708 + + - description: BCM53016 based boards + items: + - enum: + - meraki,mr32 - const: brcm,bcm53016 - const: brcm,bcm4708 From 69bb5c6f3f41fe6baa86a775c8a3e69dd27f85d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:21 +0300 Subject: [PATCH 0092/1268] ARM: dts: BCM5301X: Fix compatible strings for BCM53012 and BCM53016 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix compatible strings for devicetrees using the BCM53012 and BCM53016 SoC. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- arch/arm/boot/dts/bcm953012er.dts | 2 +- arch/arm/boot/dts/bcm953012hr.dts | 2 +- arch/arm/boot/dts/bcm953012k.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 66c64a6ec414..daca63f25134 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -13,7 +13,7 @@ #include / { - compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; model = "Meraki MR32"; chosen { diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 52feca0fb906..dd63a148a16b 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -37,7 +37,7 @@ / { model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; memory@0 { device_type = "memory"; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 9140be7ec053..b070b69466bd 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -37,7 +37,7 @@ / { model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index de40bd59a5fa..f1e6bcaa1edd 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -36,7 +36,7 @@ / { model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; aliases { serial0 = &uart0; From 0346e33d558c3372a5f8138ad8086f9414177a06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:22 +0300 Subject: [PATCH 0093/1268] dt-bindings: arm: bcm: add bindings for Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Asus RT-AC88U under BCM47094 based boards. Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 8a97ee048053..8b7e87fb6c34 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -64,6 +64,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac88u - dlink,dir-885l - linksys,panamera - luxul,abr-4500-v1 From 4db7a4d7efe5cd249967e8867bf227ec5d9edb8e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 12 Mar 2022 17:08:53 +0530 Subject: [PATCH 0094/1268] ARM: dts: ste-dbx: Update spi clock-names property Now that spi pl022 binding only accept "sspclk" as clock name, ST ericsson platform with "SSPCLK" clock name start raising dtbs_check warnings. Make necessary changes to update this property in order to make it compliant with binding. clock-names:0: 'sspclk' was expected Signed-off-by: Kuldeep Singh Link: https://lore.kernel.org/r/20220312113853.63446-5-singh.kuldeep87k@gmail.com Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index dc0bcc7020f1..c28b32640254 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -772,7 +772,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -790,7 +790,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -807,7 +807,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -824,7 +824,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -841,7 +841,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; From 1034eb1a6ab812b5c20063a0002de0b3b7f1d9ce Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 23 Feb 2022 00:33:12 +0100 Subject: [PATCH 0095/1268] dt-bindings: arm: ux500: Document Codina-TMO This is a U8500-based phone named Samsung Galaxy Exhibit or Samsung SGH-T599, codenamed "Codina TMO" as it was made for T-Mobile. Cc: phone-devel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220222233313.1774416-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/ux500.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml index a46193ad94e0..17accb31bca0 100644 --- a/Documentation/devicetree/bindings/arm/ux500.yaml +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -40,6 +40,11 @@ properties: - const: samsung,codina - const: st-ericsson,u8500 + - description: Samsung Galaxy Exhibit (SGH-T599) + items: + - const: samsung,codina-tmo + - const: st-ericsson,u8500 + - description: Samsung Galaxy Beam (GT-I8530) items: - const: samsung,gavini From 8388234ec562d77128ab9dbc6d26dff0c7b13af0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 23 Feb 2022 00:33:13 +0100 Subject: [PATCH 0096/1268] ARM: dts: ux500: Add Codina TMO device tree This adds a device tree for "Codina TMO" also known as Samsung Galaxy Exhibit or Samsung SGH-T599. It is quite different from the vanilla Codina despite sharing the same board file in the vendor tree. Fix up some comments in the Codina DTS while we're at it. Cc: phone-devel@vger.kernel.org Cc: Markuss Broks Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220222233313.1774416-2-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/ste-ux500-samsung-codina-tmo.dts | 781 ++++++++++++++++++ .../arm/boot/dts/ste-ux500-samsung-codina.dts | 8 +- 3 files changed, 788 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..fdec7b7bf26d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1382,6 +1382,7 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ux500-samsung-janice.dtb \ ste-ux500-samsung-gavini.dtb \ ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ ste-ux500-samsung-skomer.dtb \ ste-ux500-samsung-kyle.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts new file mode 100644 index 000000000000..80ae6ad05985 --- /dev/null +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, + * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively + * for T-Mobile in the United States. + * + * This phone is closely related to the Codina, but has: + * - No CPU speed cap, full ~1GHz rate + * - Different power management IC, AB8505 + * - As AB8505 has a micro USB phy, no TI TSU6111 + * - Different power routing such as the removal of the external LDO for the + * touchscreen in favor of using the AB8505 + * - Using a regulator for the key backlight LED + * - Using the Samsung S6D27A1 panel by default + * - The panel is using one of the ordinary AB8505 regulators for 1.8V + * - WiFi/Bluetooth combi chip upgraded to BCM4334 + * - GPIO for backlight control moved from 68 to 69 + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Exhibit (SGH-T599)"; + compatible = "samsung,codina-tmo", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both the 3.0V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V + default-state = "on"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO69 is used on Codina R0.4 and Codina TMO */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + }; + }; + + spi-gpio-0 { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&ab8500_ldo_aux6_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + uart@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to AB8505 */ + uart@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + /* This is mostly identical to the Codina v0.4 regulators */ + regulator { + ab8500_ldo_aux1 { + regulator-name = "v-sensors-vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "v-aux2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "v-mmc-sd"; + }; + + ab8500_ldo_aux4 { + regulator-name = "v-aux4"; + /* + * Providing some span here makes the touchkey + * LEDs actually dimmable. + */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "v-aux5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + /* 1.8 V to the display */ + regulator-name = "v-aux6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "v-sensors-vio"; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tmd2672_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + /* Bosch BMA254 accelerometer */ + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V + vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMD2672 */ + tmd2672 { + tmd2672_codina_default: tmd2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 1c1725d31c7c..8284560a7bab 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -9,9 +9,13 @@ * the boot loader. * * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). - * The GT-I8160 plain is knonw as the "europe" variant. - * The GT-I8160P appears to not use the ST Microelectronics accelerometer. + * The GT-I8160 plain is known as the "europe" variant. + * The GT-I8160P is the CDMA version and it appears to not use the ST + * Microelectronics accelerometer and reportedly has NFC mounted. * The GT-I8160chn appears to be the same as the europe variant. + * + * There is also the Codina-TMO, Samsung SGH-T599, which has its own device + * tree. */ /dts-v1/; From 003cac14f543cc3475255f10cfd6fa150c5c0e3e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 16 Feb 2022 00:46:27 +0100 Subject: [PATCH 0097/1268] ARM: dts: ux500: Register Amstaos proximity sensor The proximity sensor on the Codina is actually an Amstaos TMD2672, not Mouser, so alter the DTS to reflect this. Tested successfully with the IIO driver. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 8284560a7bab..e6ea63d23d26 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -519,10 +519,9 @@ pinctrl-0 = <&i2c0_a_1_default>; pinctrl-1 = <&i2c0_a_1_sleep>; - /* TODO: write bindings and driver for this proximity sensor */ proximity@39 { - /* Codina has the Mouser TMD2672 */ - compatible = "mouser,tmd2672"; + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; clock-frequency = <400000>; reg = <0x39>; From 5c7502397e0ccd5fa9dd762223ed29641355947b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 26 Feb 2022 02:29:48 +0100 Subject: [PATCH 0098/1268] ARM: dts: ux500: Add line impedance to fuel gauge The line impedance is used to improve battery capacity estimation. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-kyle.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 4 ++++ 7 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts index 80ae6ad05985..d6940e0afa86 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -410,6 +410,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + /* This is mostly identical to the Codina v0.4 regulators */ regulator { ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index e6ea63d23d26..acbe43269c38 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -487,6 +487,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index fd170974765f..53062d50e455 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -456,6 +456,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <43000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 290ab59e863d..b0dce91aff4b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -304,6 +304,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { regulator-name = "sensor_3v"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 42762bfcd878..16f61d8acf4c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -504,6 +504,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <15000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 2a5bf54137ce..c57676faf181 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -325,6 +325,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index dcb03ce7cbd4..dcdec867f24d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -305,6 +305,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <16000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ From a4b75fe8e1c15c96c4eb083e211ccbbfd56599f9 Mon Sep 17 00:00:00 2001 From: Jan Engelhardt Date: Tue, 28 Dec 2021 20:57:37 +0100 Subject: [PATCH 0099/1268] tee: combine "config" and "menu" for TEE's menuconfig Don't let TEE occupy two lines in menuconfig when practically no other (sub)menu does either. Signed-off-by: Jan Engelhardt Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/Kconfig | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig index e99d840c2511..73a147202e88 100644 --- a/drivers/tee/Kconfig +++ b/drivers/tee/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # Generic Trusted Execution Environment Configuration -config TEE +menuconfig TEE tristate "Trusted Execution Environment support" depends on HAVE_ARM_SMCCC || COMPILE_TEST || CPU_SUP_AMD select CRYPTO @@ -13,10 +13,7 @@ config TEE if TEE -menu "TEE drivers" - source "drivers/tee/optee/Kconfig" source "drivers/tee/amdtee/Kconfig" -endmenu endif From 3e47235eaee09488c7e467b9aaccb7c93c862c6b Mon Sep 17 00:00:00 2001 From: Phil Chang Date: Fri, 25 Feb 2022 23:20:40 +0800 Subject: [PATCH 0100/1268] tee: make tee_shm_register_kernel_buf vmalloc supported In some low-memory devices, it's hard to aquire large-orders pages, this patch allowed user using scatter pages to register shm. Signed-off-by: Phil Chang Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/optee/call.c | 2 +- drivers/tee/tee_shm.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/tee/optee/call.c b/drivers/tee/optee/call.c index bd49ec934060..2082e632adff 100644 --- a/drivers/tee/optee/call.c +++ b/drivers/tee/optee/call.c @@ -362,7 +362,7 @@ int optee_check_mem_type(unsigned long start, size_t num_pages) * Allow kernel address to register with OP-TEE as kernel * pages are configured as normal memory only. */ - if (virt_addr_valid(start)) + if (virt_addr_valid(start) || is_vmalloc_addr((void *)start)) return 0; mmap_read_lock(mm); diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index f31e29e8f1ca..836872467dc6 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -23,22 +23,37 @@ static void shm_put_kernel_pages(struct page **pages, size_t page_count) static int shm_get_kernel_pages(unsigned long start, size_t page_count, struct page **pages) { - struct kvec *kiov; size_t n; int rc; - kiov = kcalloc(page_count, sizeof(*kiov), GFP_KERNEL); - if (!kiov) - return -ENOMEM; + if (is_vmalloc_addr((void *)start)) { + struct page *page; - for (n = 0; n < page_count; n++) { - kiov[n].iov_base = (void *)(start + n * PAGE_SIZE); - kiov[n].iov_len = PAGE_SIZE; + for (n = 0; n < page_count; n++) { + page = vmalloc_to_page((void *)(start + PAGE_SIZE * n)); + if (!page) + return -ENOMEM; + + get_page(page); + pages[n] = page; + } + rc = page_count; + } else { + struct kvec *kiov; + + kiov = kcalloc(page_count, sizeof(*kiov), GFP_KERNEL); + if (!kiov) + return -ENOMEM; + + for (n = 0; n < page_count; n++) { + kiov[n].iov_base = (void *)(start + n * PAGE_SIZE); + kiov[n].iov_len = PAGE_SIZE; + } + + rc = get_kernel_pages(kiov, page_count, 0, pages); + kfree(kiov); } - rc = get_kernel_pages(kiov, page_count, 0, pages); - kfree(kiov); - return rc; } From 330e01653ac13e2e51896e3843e4969017b6d28f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 5 Mar 2022 00:37:37 +0100 Subject: [PATCH 0101/1268] ARM: dts: ux500: Add GPS to Janice device tree This adds the CSR GSD4t GPS to the Janice device tree. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-janice.dts | 40 ++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 16f61d8acf4c..e6d4fd0eb5f4 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -485,7 +485,26 @@ /* CTS/RTS is not used, CTS is repurposed as GPIO */ pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + + gnss { + /* + * The Low Noise Amplifier (LNA) power and enablement is controlled + * autonomously by the GSD4t. + * Janice has a SiRFstarIV-based GSD4t + * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. + */ + compatible = "csr,gsd4t"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO96 */ + sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gsd4t_janice_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -945,4 +964,23 @@ }; }; }; + gsd4t { + gsd4t_janice_default: gsd4t_janice { + /* Reset line, start out asserted */ + janice_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + janice_cfg2 { + pins = "GPIO96_D8"; + ste,config = <&gpio_out_lo>; + }; + /* Unused power enablement line, used in R0.0 and R0.1 boards */ + janice_cfg3 { + pins = "GPIO86_C6"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; From 973a9ba5fe489bcb323cc4f4e9ece3959dd50686 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 5 Mar 2022 00:36:03 +0100 Subject: [PATCH 0102/1268] ARM: dts: ux500: Add GPS to Skomer device tree Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-skomer.dts | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index dcdec867f24d..81b341a5ae45 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -281,12 +281,27 @@ }; }; - /* GPF UART */ + /* GPS UART */ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_skomer_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -653,6 +668,20 @@ }; }; }; + g05ta03 { + g05ta03_skomer_default: g05ta03 { + /* Reset line, start out de-asserted */ + skomer_cfg1 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + skomer_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { From 236b8cfac4e3f007b9c4f014b3d25e63cc376ef7 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Wed, 23 Mar 2022 10:56:01 -0300 Subject: [PATCH 0103/1268] arm64: dts: imx8mn-bsh-smm-s2pro: Add tlv320aic31xx audio card node BSH SystemMaster (SMM) S2 PRO board comes with an audio card based on tlv320aic31xx family codec. The audio card exposes two playback devices, one of them using the EASRC (Enhanced Asynchronous Sample Rate Converter) module. Note that this would require SDMA and EASRC firmware in order to work. Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mn-bsh-smm-s2pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index c6a8ed6745c1..fbbb3367037b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn-bsh-smm-s2-common.dtsi" +#include / { model = "BSH SMM S2 PRO"; @@ -16,6 +17,65 @@ device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; + + sound-tlv320aic31xx { + compatible = "fsl,imx-audio-tlv320aic31xx"; + model = "tlv320aic31xx-hifi"; + audio-cpu = <&sai3>; + audio-codec = <&tlv320dac3101>; + audio-asrc = <&easrc>; + audio-routing = + "Ext Spk", "SPL", + "Ext Spk", "SPR"; + mclk-id = ; + }; + + vdd_input: vdd_input { + compatible = "regulator-fixed"; + regulator-name = "vdd_input"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + fsl,asrc-format = <10>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320dac3101: audio-codec@18 { + compatible = "ti,tlv320dac3101"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dac_rst>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <&buck4_reg>; + SPRVDD-supply = <&vdd_input>; + SPLVDD-supply = <&vdd_input>; + AVDD-supply = <&buck4_reg>; + IOVDD-supply = <&buck4_reg>; + DVDD-supply = <&buck5_reg>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + ai31xx-micbias-vg = ; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; }; /* eMMC */ @@ -30,6 +90,36 @@ }; &iomuxc { + pinctrl_dac_rst: dacrstgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 From 583f24ae42a0786dbb70fde03a3652059811a9c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Feb 2022 01:17:38 +0100 Subject: [PATCH 0104/1268] arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC Add support for Data Modul i.MX8M Mini eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, PCIe, SPI NOR, USB host and USB OTG. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-data-modul-edm-sbc.dts | 996 ++++++++++++++++++ 2 files changed, 997 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7f51b537df40..52ce0f798657 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts new file mode 100644 index 000000000000..154116d01c94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -0,0 +1,996 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Marek Vasut + */ + +/dts-v1/; + +#include +#include +#include "imx8mm.dtsi" + +/ { + model = "Data Modul i.MX8M Mini eDM SBC"; + compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + /* There are 1/2/4 GiB options, adjusted by bootloader. */ + reg = <0x0 0x40000000 0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_backlight>; + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 5000000>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + panel: panel { + backlight = <&backlight>; + power-supply = <®_panel_vcc>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vcc_reg>; + regulator-name = "PANEL_VCC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 6 0>; + enable-active-high; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + enable-active-high; + }; + + watchdog-gpio { + /* TPS3813 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog_gpio>; + compatible = "linux,wdt-gpio"; + always-enabled; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + hw_algo = "level"; + /* Reset triggers in 2..3 seconds */ + hw_margin_ms = <1500>; + /* Disabled by default */ + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { /* W25Q128FVSI */ + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&ecspi2 { /* Feature connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless feature board plugged in. */ + status = "disabled"; +}; + +&ecspi3 { /* Display connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&fec1_phy>; + phy-supply = <&buck4_reg>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + fec1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "ENET_RST#", "WDOG_B#", "PMIC_INT#", + "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#", + "WDOG_KICK#", "M2-B_PCIE_CLKREQ#", + "USB1_OTG_ID_3V3", "ENET_WOL#", + "", "", "", "ENET_INT#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#", + "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#", + "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#", + "MEMCFG0", "WDOG_EN", + "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#", + "", "", "", "", + "", "", "", "SD2_RESET#", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", + "CSI_PD_1V8", "CSI_RESET_1V8#", "", "", + "", "", "", "", + "", "", "", "M2-B_WAKE_WWAN_1V8#", + "M2-B_RESET_1V8#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "NC0", "NC1", "BOOTCFG0", "BOOTCFG1", + "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5", + "BOOTCFG6", "BOOTCFG7", "NC10", "NC11", + "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11", + "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15", + "NC20", "", "", "", + "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27", + "DIS_USB_DN2", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03", + "GPIO5_IO04", "", "", "", + "", "SPI1_CS#", "", "", + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", + "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "", + "", "SPI3_CS#", "", "", "", "", "", ""; +}; + +&i2c1 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + rohm,reset-snvs-powered; + + /* + * i.MX 8M Mini Data Sheet for Consumer Products + * 3.1.3 Operating ranges + * MIMX8MM4DVTLZAA + */ + regulators { + /* VDD_SOC */ + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <950000>; + }; + + /* VDD_DRAM, BUCK5 */ + buck3_reg: BUCK3 { + regulator-name = "buck3"; + /* 1.5 GHz DDR bus clock */ + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 3V3_VDD, BUCK6 */ + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDD, BUCK7 */ + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V1_NVCC_DRAM, BUCK8 */ + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_NVCC_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V8_VDD_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDDA */ + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V9_VDD_PHY */ + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V2_VDD_PHY */ + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + compatible = "microchip,usb2514bi"; + reg = <0x2c>; + individual-port-switching; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + self-powered; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "st,m41t62"; + reg = <0x68>; + interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pcieclk: clk@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&i2c3 { /* Display connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { /* Feature connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, + <&pinctrl_panel_expansion>; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* ENET_RST# */ + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6 + /* ENET_WOL# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090 + /* ENET_INT# */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090 + >; + }; + + pinctrl_hog_feature: hog-feature-grp { + fsl,pins = < + /* GPIO4_IO27 */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006 + /* GPIO5_IO03 */ + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006 + /* GPIO5_IO04 */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006 + + /* CAN_INT# */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090 + /* CAN_RST# */ + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26 + >; + }; + + pinctrl_hog_panel: hog-panel-grp { + fsl,pins = < + /* GRAPHICS_GPIO0_1V8 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26 + >; + }; + + pinctrl_hog_misc: hog-misc-grp { + fsl,pins = < + /* PG_V_IN_VAR# */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000 + /* CSI_PD_1V8 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0 + /* CSI_RESET_1V8# */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0 + + /* DIS_USB_DN1 */ + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0 + /* DIS_USB_DN2 */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0 + + /* EEPROM_WP_1V8# */ + MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100 + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* GRAPHICS_PRSNT_1V8# */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000 + + /* CLK_CCM_CLKO1_3V3 */ + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10 + >; + }; + + pinctrl_hog_sbc: hog-sbc-grp { + fsl,pins = < + /* MEMCFG[0..2] straps */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140 + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140 + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140 + + /* BOOT_CFG[0..15] straps */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000 + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000 + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000 + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000 + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000 + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000 + + /* Not connected pins */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0 + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0 + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84 + >; + }; + + pinctrl_panel_backlight: panel-backlight-grp { + fsl,pins = < + /* BL_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104 + >; + }; + + pinctrl_panel_expansion: panel-expansion-grp { + fsl,pins = < + /* DSI_RESET_1V8# */ + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2 + /* DSI_IRQ_1V8# */ + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090 + >; + }; + + pinctrl_panel_vcc_reg: panel-vcc-grp { + fsl,pins = < + /* TFT_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104 + >; + }; + + pinctrl_panel_pwm: panel-pwm-grp { + fsl,pins = < + /* BL_PWM_3V3 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12 + >; + }; + + pinctrl_pcie0: pcie-grp { + fsl,pins = < + /* M2-B_RESET_1V8# */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102 + /* M2-B_PCIE_RST# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2 + /* M2-B_FULL_CARD_PWROFF_1V8# */ + MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102 + /* M2-B_W_DISABLE1_WWAN_1V8# */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102 + /* M2-B_W_DISABLE2_GPS_1V8# */ + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102 + /* CLK_M2_32K768 */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14 + /* M2-B_WAKE_WWAN_1V8# */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140 + /* M2-B_PCIE_WAKE# */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140 + /* M2-B_PCIE_CLKREQ# */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140 + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + /* RTC_IRQ# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090 + >; + }; + + pinctrl_sai5: sai5-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb_hub: usb-hub-grp { + fsl,pins = < + /* USBHUB_RESET# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4 + >; + }; + + pinctrl_usb_otg1: usb-otg1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000 + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090 + >; + }; + + pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_watchdog_gpio: watchdog-gpio-grp { + fsl,pins = < + /* WDOG_B# */ + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26 + /* WDOG_EN -- ungate WDT RESET# signal propagation */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6 + /* WDOG_KICK# / WDI */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26 + >; + }; +}; + +&pcie_phy { + fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */ + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcieclk 0>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_pwm>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + fsl,sai-mclk-direction-output; + /* Input into codec PLL */ + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&uart3 { /* A53 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* M4 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + /* UART4 is reserved for CM and RDC blocks CA access to UART4. */ + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* MicroSD */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vcc>; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <&buck4_reg>; + vqmmc-supply = <&buck5_reg>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; From e931a6f79620c2cc0e9dde215e35f016a3be33f4 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:05 +0100 Subject: [PATCH 0105/1268] ARM: dts: imx6qdl-vicut1/vicutgo: Set default backlight brightness to maximum Recover default behavior of the device and set maximal brightness Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 227c952543d4..e6134efbfabd 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -28,7 +28,7 @@ pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 1ac7e13249d2..c1d06bc28c67 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -23,7 +23,7 @@ pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; From 156a722b39315e95dd018dbc614e2becf4782237 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:06 +0100 Subject: [PATCH 0106/1268] ARM: dts: imx6qdl-vicut1/vicutgo: Rename backlight to backlight_lcd We have two backlight sources on this boards. Use more specific name for the LCD backlight to see the difference. Signed-off-by: David Jander Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index e6134efbfabd..833340c30537 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -21,7 +21,7 @@ stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -100,7 +100,7 @@ panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c1d06bc28c67..a1fbbc9c26b6 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -16,7 +16,7 @@ stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -102,7 +102,7 @@ panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { From 98efa526a0c436efea4cdc834ab632f66f13ac0b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:07 +0100 Subject: [PATCH 0107/1268] ARM: dts: imx6qdl-vicut1/vicutgo: Add backlight_led node backlight_led is the dimmable backlight for the rubber border on the case. It is also used to highlight the power- and some other buttons. MX6QDL_PAD_SD4_DAT1__PWM3_OUT is also assigned as output for pwm3. Since we need pwm3 for the backlight, we're forced to disable user space hardware revision detection. The bootloader will have to supply this information (i.e. through device tree). Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 24 +++++++++---------- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 33 +++++++++++++++++---------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 833340c30537..d542ddad4e32 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -33,6 +33,15 @@ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -392,8 +401,8 @@ &gpio2 { gpio-line-names = "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", "POWER_LED", "", "", "", "", "", "", ""; }; @@ -778,17 +787,6 @@ /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 is shared with PWM3 */ - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a1fbbc9c26b6..2f6b263eea66 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -28,6 +28,15 @@ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -448,6 +457,12 @@ status = "okay"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &ssi1 { #sound-dai-cells = <0>; fsl,mode = "ac97-slave"; @@ -669,18 +684,6 @@ /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 @@ -738,6 +741,12 @@ >; }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + /* YaCO AUX Uart */ pinctrl_uart1: uart1grp { fsl,pins = < From cb15ebbc10b5d35af76f34f18b1592abc39c3f5b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:08 +0100 Subject: [PATCH 0108/1268] ARM: dts: imx6qdl-vicut1: update gpio-line-names for some GPIOs countedX lines have different board names (YACO_x). And REV_ and BOARD_ pins have multiple functions. So, use names exposed to the OS. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 2f6b263eea66..ec39008c0950 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -277,9 +277,9 @@ &gpio2 { gpio-line-names = - "count0", "count1", "count2", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "", "ON_SWITCH", "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; }; @@ -298,8 +298,10 @@ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "BL_EN", "BL_PWM", "", ""; + "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "ON1_CTRL", + "ON2_CTRL", "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; }; &gpio5 { From 05ed0bc09a5377825b37240c0212a894aa4dad49 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:10 +0100 Subject: [PATCH 0109/1268] ARM: dts: imx6dl-victgo: Add interrupt-counter nodes Interrupt counter is mainlined, now we can add missing counter nodes. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 41 ++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index d542ddad4e32..3d6dc1b2c5e9 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -54,6 +54,27 @@ }; }; + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -400,7 +421,7 @@ &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", @@ -708,6 +729,24 @@ >; }; + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 From e310ba3c0fd5d9d017831501e81dad7e5a9aa2d7 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:11 +0100 Subject: [PATCH 0110/1268] ARM: dts: imx6dl-victgo: The TGO uses a lg,lb070wv8 compatible 7" display This series of devices is using lg,lb070wv8 instead of kyo,tcg121xglp. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 3d6dc1b2c5e9..7a29283da245 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -129,7 +129,7 @@ }; panel { - compatible = "kyo,tcg121xglp"; + compatible = "lg,lb070wv8"; backlight = <&backlight_lcd>; power-supply = <®_3v3>; From 7bb9b9e34b8742afc0cd8547103ef0106012947b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:12 +0100 Subject: [PATCH 0111/1268] ARM: dts: imx6qdl-victgo: add CAN termination support The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So, remove wrong regulator and assign this gpio to new DT CAN termination property. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7a29283da245..7dd7fb165432 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -160,15 +160,6 @@ regulator-max-microvolt = <3300000>; }; - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; regulator-name = "otg-vbus"; @@ -312,6 +303,8 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; status = "okay"; }; @@ -648,7 +641,6 @@ }; &usbh1 { - vbus-supply = <®_h1_vbus>; pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; From 1c6add99c2bf1b19175e80826534b025c967afdd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:27 +0100 Subject: [PATCH 0112/1268] arm64: dts: imx8mm-kontron: fix ethernet node name The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Acked-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index d40caf14ac4a..23be1ec538ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -182,7 +182,7 @@ #address-cells = <1>; #size-cells = <0>; - usbnet: usbether@1 { + usbnet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; From 942501661fa65f13bf9b5582e8248e92770b2d93 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Thu, 24 Mar 2022 17:38:48 +0530 Subject: [PATCH 0113/1268] soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194 Add nvmem cell lookup entries for below FUSE cells: - gcplex-config-fuse - pdi0 - pdi1 Also include the device name prefix "gpu-" in the names of the GPU FUSE cells in nvmem_cell_info. Signed-off-by: Sagar Kamble Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 8 ++++---- drivers/soc/tegra/fuse/fuse-tegra30.c | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index aa94fda282f4..b0a8405dbdb1 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. */ #include @@ -162,7 +162,7 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bit_offset = 0, .nbits = 32, }, { - .name = "gcplex-config-fuse", + .name = "gpu-gcplex-config-fuse", .offset = 0x1c8, .bytes = 4, .bit_offset = 0, @@ -186,13 +186,13 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bit_offset = 0, .nbits = 32, }, { - .name = "pdi0", + .name = "gpu-pdi0", .offset = 0x300, .bytes = 4, .bit_offset = 0, .nbits = 32, }, { - .name = "pdi1", + .name = "gpu-pdi1", .offset = 0x304, .bytes = 4, .bit_offset = 0, diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index b071d433d74f..f01d8a2547b6 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. */ #include @@ -344,6 +344,21 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { .cell_name = "xusb-pad-calibration-ext", .dev_id = "3520000.padctl", .con_id = "calibration-ext", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-gcplex-config-fuse", + .dev_id = "17000000.gpu", + .con_id = "gcplex-config-fuse", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-pdi0", + .dev_id = "17000000.gpu", + .con_id = "pdi0", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-pdi1", + .dev_id = "17000000.gpu", + .con_id = "pdi1", }, }; From 7b8861d8e6279a27873b85e3786fba8706fde7c9 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:42 +0100 Subject: [PATCH 0114/1268] ARM: dts: imx6ul: add TQ-Systems MBa6ULx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi | 211 +++++++ arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts | 55 ++ arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi | 37 ++ arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts | 15 + arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi | 71 +++ arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi | 43 ++ arch/arm/boot/dts/mba6ulx.dtsi | 571 ++++++++++++++++++ 8 files changed, 1005 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi create mode 100644 arch/arm/boot/dts/mba6ulx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..c76742cfe5b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -690,6 +690,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-kontron-n6310-s.dtb \ imx6ul-kontron-n6310-s-43.dtb \ imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi new file mode 100644 index 000000000000..eca94ed6451b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULxL + * - TQMa6ULLx + * - TQMa6ULLxL + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature-sensor@1a { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi new file mode 100644 index 000000000000..fc38e185a51e --- /dev/null +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button1 { + label = "s14"; + linux,code = ; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s6"; + linux,code = ; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s7"; + linux,code = ; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "POWER"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; From a333f3e46d76ecbe1cb8337fade76ee0d8514a8a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:43 +0100 Subject: [PATCH 0115/1268] ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 +++++++++++++++++++ .../arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c76742cfe5b1..e991232ae943 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -692,6 +692,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-tqma6ul1-mba6ulx.dtb \ imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..caf2c5d03f7e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; From 05c44ed0b776170fdf031080463cb5abd62cbed8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:44 +0100 Subject: [PATCH 0116/1268] ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e991232ae943..df272d658031 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..326e6da91ed4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From cbff1ae6bf3b9ecf0f4bf6afc509ce4b9aa70191 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:45 +0100 Subject: [PATCH 0117/1268] ARM: dts: imx6ull: add TQ-Systems MBa6ULLxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index df272d658031..aec4196d56fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -714,6 +714,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..8e4d5cd18614 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From d3ed7526543db9d26341b9df97064b332262b626 Mon Sep 17 00:00:00 2001 From: Sandipan Patra Date: Fri, 1 Apr 2022 20:03:43 +0530 Subject: [PATCH 0118/1268] soc/tegra: pmc: Update Tegra234 reset sources Update the tegra234_reset_sources array to contain all reset sources for Tegra234 and NULL out the entries that do not actually exist. Signed-off-by: Sandipan Patra Reviewed-by: Andy Shevchenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fdf508e03400..c01db5309b5e 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3766,7 +3766,7 @@ static const struct tegra_pmc_regs tegra234_pmc_regs = { }; static const char * const tegra234_reset_sources[] = { - "SYS_RESET_N", + "SYS_RESET_N", /* 0x0 */ "AOWDT", "BCCPLEXWDT", "BPMPWDT", @@ -3774,19 +3774,36 @@ static const char * const tegra234_reset_sources[] = { "SPEWDT", "APEWDT", "LCCPLEXWDT", - "SENSOR", - "AOTAG", - "VFSENSOR", + "SENSOR", /* 0x8 */ + NULL, + NULL, "MAINSWRST", "SC7", "HSM", - "CSITE", + NULL, "RCEWDT", - "PVA0WDT", - "PVA1WDT", - "L1A_ASYNC", + NULL, /* 0x10 */ + NULL, + NULL, "BPMPBOOT", "FUSECRC", + "DCEWDT", + "PSCWDT", + "PSC", + "CSITE_SW", /* 0x18 */ + "POD", + "SCPM", + "VREFRO_POWERBAD", + "VMON", + "FMON", + "FSI_R5WDT", + "FSI_THERM", + "FSI_R52C0WDT", /* 0x20 */ + "FSI_R52C1WDT", + "FSI_R52C2WDT", + "FSI_R52C3WDT", + "FSI_FMON", + "FSI_VMON", /* 0x25 */ }; static const struct tegra_wake_event tegra234_wake_events[] = { From 0b08af343ab0b2dc53f34e7b2c7b98562b60cc93 Mon Sep 17 00:00:00 2001 From: Alexander Bauer Date: Tue, 22 Feb 2022 10:16:05 +0100 Subject: [PATCH 0119/1268] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or NAND. Supported features: * eMMC/NAND * i2c RTC * i2c TEMP * PMIC * PWM * debug UART * CAN * SD card * 2x 1Gbit Ethernet * RS232/RS485 * USB 2.0 Host * TPM * SPI-NOR Signed-off-by: Alexander Bauer Signed-off-by: Jens Lang Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 588 ++++++++++++++++++ 4 files changed, 630 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aec4196d56fc..252353fb4e3b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..5464a52a1f94 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; From 8bcbcbba9109d6e26029c089826b708164a2cb12 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 22 Feb 2022 10:16:06 +0100 Subject: [PATCH 0120/1268] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Instead of changing default pwm-cells property, use the default "#pwm-cells = <3>" and add the third option. Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..6ce534a896ef 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -91,7 +91,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; From 1cfa1e68af8d40ab233d5d27bc8446e4c5107571 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:29 +0100 Subject: [PATCH 0121/1268] arm64: dts: imx8mn-evk: use proper names for PMIC outputs Use the power signal names as given in the schematics of the reference board. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index b4225cfcb6d9..2b685c0c7eeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -41,7 +41,7 @@ regulators { buck1: BUCK1{ - regulator-name = "BUCK1"; + regulator-name = "VDD_SOC"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -50,7 +50,7 @@ }; buck2: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "VDD_ARM_0V9"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -61,7 +61,7 @@ }; buck4: BUCK4{ - regulator-name = "BUCK4"; + regulator-name = "VDD_3V3"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -69,7 +69,7 @@ }; buck5: BUCK5{ - regulator-name = "BUCK5"; + regulator-name = "VDD_1V8"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -77,7 +77,7 @@ }; buck6: BUCK6 { - regulator-name = "BUCK6"; + regulator-name = "NVCC_DRAM_1V1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -85,7 +85,7 @@ }; ldo1: LDO1 { - regulator-name = "LDO1"; + regulator-name = "NVCC_SNVS_1V8"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -93,7 +93,7 @@ }; ldo2: LDO2 { - regulator-name = "LDO2"; + regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; @@ -101,7 +101,7 @@ }; ldo3: LDO3 { - regulator-name = "LDO3"; + regulator-name = "VDDA_1V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -109,7 +109,7 @@ }; ldo4: LDO4 { - regulator-name = "LDO4"; + regulator-name = "VDD_PHY_1V2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -117,7 +117,7 @@ }; ldo5: LDO5 { - regulator-name = "LDO5"; + regulator-name = "NVCC_SD2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; From bc046b952a5494b0dc53be28779460cee1214a3f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:30 +0100 Subject: [PATCH 0122/1268] arm64: dts: imx8mn-evk: fix the min/max voltages of the PMIC Use the proper voltages as supported by the board instead of the ones supported by the PMIC. The voltages were taken from both the schematic of the 8MNANOLPD4-EVK eval board and the datasheet of the IMX8MN SoC. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 34 ++++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 2b685c0c7eeb..4eb467df5ba7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -42,8 +42,8 @@ regulators { buck1: BUCK1{ regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -51,8 +51,8 @@ buck2: BUCK2 { regulator-name = "VDD_ARM_0V9"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -62,32 +62,32 @@ buck4: BUCK4{ regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -95,23 +95,23 @@ ldo2: LDO2 { regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "VDD_PHY_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-boot-on; regulator-always-on; }; From 7ac853ba789d1d9fb22b05f4ebd3a37fd1bb11c1 Mon Sep 17 00:00:00 2001 From: Aniruddha Rao Date: Wed, 16 Mar 2022 15:14:45 +0530 Subject: [PATCH 0123/1268] arm64: tegra: Update SDMMC1/3 clock source for Tegra194 The default parent for SDMMC1/3 clock sources can provide maximum frequency of 136MHz for SDR104 mode. Update parent clock source for SDMMC1/SDMMC3 instances to increase the output clock frequency to 195MHz and improve the perf. Signed-off-by: Aniruddha Rao Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 751ebe5e9506..1d6be5774fac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -934,6 +934,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC1>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, @@ -968,6 +973,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC3>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, From 5472b7df7c795352f73e9dfa68c6e5eb5db7fac8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 17:00:01 +0800 Subject: [PATCH 0124/1268] arm64: dts: imx8mq: add hdmi phy 27m clock The i.MX8MQ PLL support hdmi phy 27m as pll reference clock, so add a fixed clock for it. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5b3e849f554d..1eca2b431467 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -63,6 +63,13 @@ clock-output-names = "osc_27m"; }; + hdmi_phy_27m: clock-hdmi-phy-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "hdmi_phy_27m"; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; From 71f69ffa0129bf04205edf0e7dc73dc4777b2588 Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Wed, 9 Mar 2022 00:00:26 +0530 Subject: [PATCH 0125/1268] arm64: tegra: Add QSPI controllers on Tegra234 This adds the QSPI controllers on the Tegra234 SoC and populates the SPI NOR flash device for the Jetson AGX Orin platform. Signed-off-by: Ashish Singhal Signed-off-by: Jon Hunter Signed-off-by: Krishna Yarlagadda Reviewed-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 12 ++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 28 +++++++++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 8 ++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d95a542c0bca..798de9226ba5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -7,6 +7,18 @@ compatible = "nvidia,p3701-0000", "nvidia,tegra234"; bus@0 { + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..448512af7dea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -654,6 +654,20 @@ reset-names = "i2c"; }; + spi@3270000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3270000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI0>; + reset-names = "qspi"; + status = "disabled"; + }; + pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; @@ -666,6 +680,20 @@ #pwm-cells = <2>; }; + spi@3300000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3300000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI1>; + reset-names = "qspi"; + status = "disabled"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8cae969e8cba..bd4c3086a2da 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -140,6 +140,14 @@ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +#define TEGRA234_CLK_QSPI0_2X_PM 192U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +#define TEGRA234_CLK_QSPI1_2X_PM 193U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +#define TEGRA234_CLK_QSPI0_PM 194U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +#define TEGRA234_CLK_QSPI1_PM 195U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 1362cd5e03f0..547ca3b60caa 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -40,6 +40,8 @@ #define TEGRA234_RESET_PWM6 73U #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U +#define TEGRA234_RESET_QSPI0 76U +#define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U From d5becc32308c31c6c88bfdf55c1ec8c537a8cdd1 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 18 Mar 2022 11:37:03 +0100 Subject: [PATCH 0126/1268] ARM: tegra: Fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index e6911a14c096..1f57e7c0feae 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -83,7 +83,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) * For warm boot CPU that was resumed from CPU hotplug, the * power will be resumed automatically after un-halting the * flow controller of the warm boot CPU. We need to wait for - * the confirmaiton that the CPU is powered then removing + * the confirmation that the CPU is powered then removing * the IO clamps. * For cold boot CPU, do not wait. After the cold boot CPU be * booted, it will run to tegra_secondary_init() and set From db85474594609fc6f6a37fe5d5001fa9341971ed Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 Apr 2022 17:40:50 +0200 Subject: [PATCH 0127/1268] dt-bindings: soc: samsung: usi: refer to dtschema for SPI After adding DT schema for Samsung SPI controller, the Samsung USI bindings can reference it directly for proper schema validation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220324134106.103588-1-krzk@kernel.org --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index a98ed66d092e..55417a649970 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -77,7 +77,7 @@ patternProperties: description: Child node describing underlying UART/serial "^spi@[0-9a-f]+$": - type: object + $ref: /schemas/spi/samsung,spi.yaml description: Child node describing underlying SPI required: From 6ded3d7471d8bb01eb87ac2d506db7e8a839986a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 6 Apr 2022 18:00:07 +0200 Subject: [PATCH 0128/1268] memory: emif: remove unneeded ENOMEM error messages Memory subsystem already prints message about failed memory allocation, there is no need to do it in the drivers. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220304082339.230938-1-krzysztof.kozlowski@canonical.com --- drivers/memory/emif.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c index ecc78d6f89ed..edf3ba7447ed 100644 --- a/drivers/memory/emif.c +++ b/drivers/memory/emif.c @@ -1025,10 +1025,8 @@ static struct emif_data *__init_or_module get_device_details( temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); - if (!emif || !temp || !dev_info) { - dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); + if (!emif || !temp || !dev_info) goto error; - } memcpy(temp, pd, sizeof(*pd)); pd = temp; @@ -1067,9 +1065,6 @@ static struct emif_data *__init_or_module get_device_details( temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); if (temp) memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); - else - dev_warn(dev, "%s:%d: allocation error\n", __func__, - __LINE__); pd->custom_configs = temp; } @@ -1084,8 +1079,6 @@ static struct emif_data *__init_or_module get_device_details( memcpy(temp, pd->timings, size); pd->timings = temp; } else { - dev_warn(dev, "%s:%d: allocation error\n", __func__, - __LINE__); get_default_timings(emif); } } else { @@ -1098,8 +1091,6 @@ static struct emif_data *__init_or_module get_device_details( memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); pd->min_tck = temp; } else { - dev_warn(dev, "%s:%d: allocation error\n", __func__, - __LINE__); pd->min_tck = &lpddr2_jedec_min_tck; } } else { From 6d41e13041a306f85ad6cbeb3d532f35cc5cc90a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:38 +0000 Subject: [PATCH 0129/1268] dt-bindings: watchdog: sunxi: fix F1C100s compatible The F1C100 series actually features a newer generation watchdog IP, so the compatible string was wrong. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-2-andre.przywara@arm.com --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 43afa24513b9..7a26cde0afdd 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -26,10 +26,8 @@ properties: - allwinner,sun50i-h616-wdt - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,suniv-f1c100s-wdt - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,suniv-f1c100s-wdt - - const: allwinner,sun4i-a10-wdt - const: allwinner,sun20i-d1-wdt - items: - const: allwinner,sun20i-d1-wdt-reset From 42b91bb160815d82d36cc1cfe28f1edd9079d912 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:39 +0000 Subject: [PATCH 0130/1268] dt-bindings: watchdog: sunxi: clarify clock support Most Allwinner SoCs have just one input clock to drive the watchdog peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down internally to 32 KHz. The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as its only clock input, which has the same effect, but let's the binding description mismatch. Change the binding description to name the clocks more loosely, so both the LOSC and divided HOSC match the description. As the fixed clock names now make less sense, drop them from SoCs supporting just one clock input, they were not used by any DT anyway. For the newer SoCs, supporting a choice of two input clocks, we keep both the description and clock-names requirement. Signed-off-by: Andre Przywara Reviewed-by: Guenter Roeck Reviewed-by: Samuel Holland Reviewed-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-3-andre.przywara@arm.com --- .../watchdog/allwinner,sun4i-a10-wdt.yaml | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 7a26cde0afdd..cbcf19f51411 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -39,14 +39,8 @@ properties: clocks: minItems: 1 items: - - description: High-frequency oscillator input, divided internally - - description: Low-frequency oscillator input, only found on some variants - - clock-names: - minItems: 1 - items: - - const: hosc - - const: losc + - description: 32 KHz input clock + - description: secondary clock source interrupts: maxItems: 1 @@ -71,9 +65,14 @@ then: properties: clocks: minItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input clock-names: - minItems: 2 + items: + - const: hosc + - const: losc required: - clock-names @@ -83,9 +82,6 @@ else: clocks: maxItems: 1 - clock-names: - maxItems: 1 - unevaluatedProperties: false examples: From 01a850ee61cbf0ab77dcbf26bb133fec2dd640d6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:40 +0000 Subject: [PATCH 0131/1268] ARM: dts: suniv: F1C100: fix watchdog compatible The F1C100 series of SoCs actually have their watchdog IP being compatible with the newer Allwinner generation, not the older one. The currently described sun4i-a10-wdt actually does not work, neither the watchdog functionality (just never fires), nor the reset part (reboot hangs). Replace the compatible string with the one used by the newer generation. Verified to work with both the watchdog and reboot functionality on a LicheePi Nano. Also add the missing interrupt line and clock source, to make it binding compliant. Fixes: 4ba16d17efdd ("ARM: dts: suniv: add initial DTSI file for F1C100s") Signed-off-by: Andre Przywara Acked-by: Guenter Roeck Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-4-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 6100d3b75f61..def830101448 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -104,8 +104,10 @@ wdt: watchdog@1c20ca0 { compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun4i-a10-wdt"; + "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; + interrupts = <16>; + clocks = <&osc32k>; }; uart0: serial@1c25000 { From fb2dcdd7c44652add88ac518c67b208e5133a7a9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:41 +0000 Subject: [PATCH 0132/1268] dt-bindings: arm: sunxi: document LicheePi Nano name The top level LicheePi Nano compatible name was never documented in the bindings, so add the currently used string. As for the manufacturer name, Samuel reports: ========== From what I can tell, "Lichee Pi Nano" [1][2] is the original board, and the "Sipeed Lichee Nano" [3] is a newer batch by some of the same people [4]. Other than the silkscreen and the addition of the resistive touchscreen IC, the boards look identical. And in fact I was able to find an intermediate version of the schematic [5] that uses the old styling but includes the touchscreen IC. ========== [1]: https://licheepizero.us/ [2]: http://nano.lichee.pro/ [3]: https://wiki.sipeed.com/hardware/en/lichee/Nano/Nano.html [4]: see e.g. http://bbs.lichee.pro/ [5]: https://github.com/hongxuyao/F1C100s_with_Keil_RTX4_emWin5/blob/spl-separated/doc/lichee-nano/lichee_nano-Schematic.pdf Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-5-andre.przywara@arm.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 086c68771d2b..95278a6a9a8e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -391,6 +391,11 @@ properties: - const: libretech,all-h5-cc-h5 - const: allwinner,sun50i-h5 + - description: Lichee Pi Nano + items: + - const: licheepi,licheepi-nano + - const: allwinner,suniv-f1c100s + - description: Lichee Pi One items: - const: licheepi,licheepi-one From 1aba2af585fc594f08e2a90e37d7f943b6d68730 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:42 +0000 Subject: [PATCH 0133/1268] ARM: dts: suniv: F1C100: add clock and reset macros Include clock and reset macros and replace magic numbers. Signed-off-by: Jesse Taube Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-6-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index def830101448..922efd5e9457 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc */ +#include +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -82,7 +85,7 @@ compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -116,8 +119,8 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -127,8 +130,8 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -138,8 +141,8 @@ interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; From a6d9efb62a482c2da1078d9654b68a0777aa2fc6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:43 +0000 Subject: [PATCH 0134/1268] ARM: dts: suniv: F1C100: fix CPU node The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing the reg property, and the corresponding address and size cells properties. Add them to make the bindings check pass. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-7-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 922efd5e9457..0a7fa37bbd24 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -29,9 +29,13 @@ }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; }; From a26123f355f23d8ba980d7ecf4899d309d5cd708 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:44 +0000 Subject: [PATCH 0135/1268] ARM: dts: suniv: F1C100: fix timer node The Allwinner F1C100s has three timer instances, each with their own interrupt line. Add the missing two interrupts to the DT node, to match the DT binding. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-8-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0a7fa37bbd24..f455e276521e 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -105,7 +105,7 @@ timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; - interrupts = <13>; + interrupts = <13>, <14>, <15>; clocks = <&osc24M>; }; From a672a3f2f0221bc56e94d6508e3b3fc74442065b Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:45 +0000 Subject: [PATCH 0136/1268] ARM: dts: suniv: F1C100: add MMC controllers The F1C100 series contains two MMC controllers, where the first one is typically connected to an (micro)SD card slot (as this is the one the BROM is able to boot from). Describe the two controllers in the SoC .dtsi. We also add the pinctrl description for MMC0, since this is the only pin set supporting that function anyway, and SD cards are very common across boards. Signed-off-by: Jesse Taube Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-9-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index f455e276521e..59e0bd952f50 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,42 @@ }; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -96,6 +132,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; From 30b6259f8bb8f17377d13c61e47b66d71ec3abfe Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:46 +0000 Subject: [PATCH 0137/1268] ARM: dts: suniv: licheepi-nano: add microSD card Enable MMC0 and supply the board setting to enable the microSD card slot on the LicheePi Nano board. Apart from the always missing write protect switch on microSD slots, the card-detect pin is not connected to anything, so we use the broken-cd property. Signed-off-by: Jesse Taube [Andre: add alias and vmmc supply] Signed-off-by: Andre Przywara Acked-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-10-andre.przywara@arm.com --- .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index a1154e6c7cb5..8fa79a1d1d2d 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -11,12 +11,28 @@ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; aliases { + mmc0 = &mmc0; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + status = "okay"; + vmmc-supply = <®_vcc3v3>; }; &uart0 { From 382e0d4f9ece6d1b282ac70c246bdc7be5edc053 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:47 +0000 Subject: [PATCH 0138/1268] dt-bindings: spi: sunxi: document F1C100 controllers The Allwinner F1C100 series contains two SPI controllers, which are compatible to the IP block used in the Allwinner H3 as well. The only difference in the integration is the missing mod clock in the F1C100, but that does not affect the SPI controller binding, as we can still supply the correct clock (AHB parent) easily. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-11-andre.przywara@arm.com --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 908248260afa..ca4c95345a49 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -26,6 +26,7 @@ properties: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi - allwinner,sun50i-h616-spi + - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi reg: From 335f57508a7a3220feb161400f0475e7f42be1b3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:48 +0000 Subject: [PATCH 0139/1268] ARM: dts: suniv: F1C100: add SPI support The F1C100 series contains two SPI controllers, and many boards use SPI0 for a SPI flash, as the BROM is able to boot from that. Describe the two controllers in the SoC .dtsi, and also add the PortC pins for SPI0, since this is where BROM looks at when trying to boot from the commonly used SPI flash. The SPI controller seems to be the same as in the H3 chips, but it lacks a separate mod clock. The manual says it's connected to AHB directly. We don't export that AHB clock directly, but can use the AHB *gate* clock as a clock source, since the SPI driver is not supposed to change the AHB frequency anyway. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-12-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 59e0bd952f50..0edc1724407b 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,34 @@ }; }; + spi0: spi@1c05000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,suniv-f1c100s-mmc", "allwinner,sun7i-a20-mmc"; @@ -138,6 +166,11 @@ drive-strength = <30>; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; From 37384b81bc255bca3412536c50598fa50d05c751 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:49 +0000 Subject: [PATCH 0140/1268] ARM: dts: suniv: licheepi-nano: add SPI flash Most LicheePi Nano boards come with soldered SPI flash, so enable SPI0 in the .dts and describe the flash chip. There is evidence of different flash chips used, also of boards with no flash chip soldered, but the Winbond 16MiB model is the most common, so use that for the compatible string. The actual flash chip model will be auto-detected at runtime anyway. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-13-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index 8fa79a1d1d2d..04e59b8381cb 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -13,6 +13,7 @@ aliases { mmc0 = &mmc0; serial0 = &uart0; + spi0 = &spi0; }; chosen { @@ -35,6 +36,20 @@ vmmc-supply = <®_vcc3v3>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pe_pins>; From 91276c0fa4b405c90d7a7fafdca84ae18a516bbf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 12:29:36 +0200 Subject: [PATCH 0141/1268] ARM: s3c24xx: remove support for ISA drivers on BAST PC/104 BAST is the one machine that theoretically supports unmodified ISA drivers for hardware on its PC/104 connector, using a custom version of the inb()/outb() and inw()/outw() macros. This is incompatible with the generic version used in asm/io.h, and can't easily be used in a multiplatform kernel. Removing the special case for 16-bit I/O port access on BAST gets us closer to multiplatform, at the expense of any PC/104 users with 16-bit cards having to either use an older kernel or modify their ISA drivers to manually ioremap() the area and use readw()/write() in place of inw()/outw(). Either way is probably ok, given that there is a recurring discussion about dropping s3c24xx altogether, and many traditional ISA drivers are already gone. Machines other than BAST already have no support for ISA drivers, though a couple of them do map one of the external chip-selects into the ISA port range, using the same address for 8-bit and 16-bit I/O. It is unlikely that anything actually uses this mapping, but it's also easy to keep this working by mapping it to the normal platform-independent PCI I/O base that is otherwise unused on s3c24xx. The mach/map-base.h file is no longer referenced in global headers and can be moved into the platform directory. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-s3c/Kconfig.s3c24xx | 1 - arch/arm/mach-s3c/cpu.c | 2 +- arch/arm/mach-s3c/include/mach/io-s3c24xx.h | 50 ------------------- arch/arm/mach-s3c/include/mach/io.h | 8 --- arch/arm/mach-s3c/irq-pm-s3c24xx.c | 2 +- arch/arm/mach-s3c/mach-anubis.c | 5 -- arch/arm/mach-s3c/mach-bast.c | 5 -- arch/arm/mach-s3c/mach-osiris.c | 5 -- arch/arm/mach-s3c/mach-rx3715.c | 6 --- arch/arm/mach-s3c/mach-smdk2416.c | 10 ---- arch/arm/mach-s3c/mach-smdk2440.c | 10 ---- arch/arm/mach-s3c/mach-smdk2443.c | 10 ---- arch/arm/mach-s3c/mach-vr1000.c | 5 -- .../mach-s3c/{include/mach => }/map-base.h | 6 +++ arch/arm/mach-s3c/map-s3c24xx.h | 2 +- arch/arm/mach-s3c/map-s3c64xx.h | 2 +- 17 files changed, 10 insertions(+), 120 deletions(-) delete mode 100644 arch/arm/mach-s3c/include/mach/io-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/io.h rename arch/arm/mach-s3c/{include/mach => }/map-base.h (87%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index faf696173af7..2242d2ae8854 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,7 +444,6 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GPIO_SAMSUNG select GPIOLIB - select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS select USE_OF diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx index 000e3e234f71..d47df6427e89 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c24xx +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -181,7 +181,6 @@ config MACH_AML_M5900 config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" - select ISA select MACH_BAST_IDE select S3C2410_COMMON_DCLK select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ diff --git a/arch/arm/mach-s3c/cpu.c b/arch/arm/mach-s3c/cpu.c index 6e9772555f0d..05a6b4be1768 100644 --- a/arch/arm/mach-s3c/cpu.c +++ b/arch/arm/mach-s3c/cpu.c @@ -10,7 +10,7 @@ #include #include -#include +#include "map-base.h" #include "cpu.h" unsigned long samsung_cpu_id; diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h deleted file mode 100644 index 738b775d3336..000000000000 --- a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H -#define __ASM_ARM_ARCH_IO_S3C24XX_H - -#include - -/* - * ISA style IO, for each machine to sort out mappings for, - * if it implements it. We reserve two 16M regions for ISA, - * so the PC/104 can use separate addresses for 8-bit and - * 16-bit port I/O. - */ -#define PCIO_BASE S3C_ADDR(0x02000000) -#define IO_SPACE_LIMIT 0x00ffffff -#define S3C24XX_VA_ISA_WORD (PCIO_BASE) -#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) - -#ifdef CONFIG_ISA - -#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) -#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) -#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) - -#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) -#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) -#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) - -#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#else - -#define __io(x) (PCIO_BASE + (x)) - -#endif - -#endif diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h deleted file mode 100644 index 30a0135708dc..000000000000 --- a/arch/arm/mach-s3c/include/mach/io.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Krzysztof Kozlowski - */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "io-s3c24xx.h" -#endif diff --git a/arch/arm/mach-s3c/irq-pm-s3c24xx.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c index 4d5e28312d91..55f41135ad70 100644 --- a/arch/arm/mach-s3c/irq-pm-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c @@ -15,7 +15,7 @@ #include "cpu.h" #include "pm.h" -#include +#include "map-base.h" #include "map-s3c.h" #include "regs-irq.h" diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 04147cc0adcc..60df40052209 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -57,11 +57,6 @@ static struct map_desc anubis_iodesc[] __initdata = { .pfn = __phys_to_pfn(0x0), .length = SZ_4M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, }, /* we could possibly compress the next set down into a set of smaller tables diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 27e8d5950228..5ac24e406157 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -75,11 +75,6 @@ static struct map_desc bast_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* bast CPLD control registers, and external interrupt controls */ { diff --git a/arch/arm/mach-s3c/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c index 3aefb9d22340..8387773f4fd4 100644 --- a/arch/arm/mach-s3c/mach-osiris.c +++ b/arch/arm/mach-s3c/mach-osiris.c @@ -58,11 +58,6 @@ static struct map_desc osiris_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C2410_CS5), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS5), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers */ diff --git a/arch/arm/mach-s3c/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c index 9fd2d9dc3689..586cb0fdfce0 100644 --- a/arch/arm/mach-s3c/mach-rx3715.c +++ b/arch/arm/mach-s3c/mach-rx3715.c @@ -48,13 +48,7 @@ static struct map_desc rx3715_iodesc[] __initdata = { /* dump ISA space somewhere unused */ - { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS3), .length = SZ_1M, diff --git a/arch/arm/mach-s3c/mach-smdk2416.c b/arch/arm/mach-s3c/mach-smdk2416.c index 4d883a792cc6..38b4a7cd4178 100644 --- a/arch/arm/mach-s3c/mach-smdk2416.c +++ b/arch/arm/mach-s3c/mach-smdk2416.c @@ -53,16 +53,6 @@ static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2440.c b/arch/arm/mach-s3c/mach-smdk2440.c index 7f6fe0db04f3..392554b1eba2 100644 --- a/arch/arm/mach-s3c/mach-smdk2440.c +++ b/arch/arm/mach-s3c/mach-smdk2440.c @@ -43,16 +43,6 @@ static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2443.c b/arch/arm/mach-s3c/mach-smdk2443.c index fc54c91ade56..4c541a03e49e 100644 --- a/arch/arm/mach-s3c/mach-smdk2443.c +++ b/arch/arm/mach-s3c/mach-smdk2443.c @@ -40,16 +40,6 @@ static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-vr1000.c b/arch/arm/mach-s3c/mach-vr1000.c index 5c3d07cf2e79..3aa8c707f8a2 100644 --- a/arch/arm/mach-s3c/mach-vr1000.c +++ b/arch/arm/mach-s3c/mach-vr1000.c @@ -67,11 +67,6 @@ static struct map_desc vr1000_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers, and external interrupt controls */ diff --git a/arch/arm/mach-s3c/include/mach/map-base.h b/arch/arm/mach-s3c/map-base.h similarity index 87% rename from arch/arm/mach-s3c/include/mach/map-base.h rename to arch/arm/mach-s3c/map-base.h index 34b39ded0e2e..463a995b399b 100644 --- a/arch/arm/mach-s3c/include/mach/map-base.h +++ b/arch/arm/mach-s3c/map-base.h @@ -33,6 +33,12 @@ #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ +/* ISA device mapping for BAST to use with inb()/outb() on 8-bit I/O. + * 16-bit I/O on BAST now requires driver modifications to manually + * ioremap CS3. + */ +#define S3C24XX_VA_ISA_BYTE PCI_IOBASE + /* This is used for the CPU specific mappings that may be needed, so that * they do not need to directly used S3C_ADDR() and thus make it easier to * modify the space for mapping. diff --git a/arch/arm/mach-s3c/map-s3c24xx.h b/arch/arm/mach-s3c/map-s3c24xx.h index b5dba78a9dd7..f8d075b11d6f 100644 --- a/arch/arm/mach-s3c/map-s3c24xx.h +++ b/arch/arm/mach-s3c/map-s3c24xx.h @@ -9,7 +9,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H -#include +#include "map-base.h" #include "map-s3c.h" /* diff --git a/arch/arm/mach-s3c/map-s3c64xx.h b/arch/arm/mach-s3c/map-s3c64xx.h index d7740d2a77c4..9de1c58bcb06 100644 --- a/arch/arm/mach-s3c/map-s3c64xx.h +++ b/arch/arm/mach-s3c/map-s3c64xx.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H __FILE__ -#include +#include "map-base.h" #include "map-s3c.h" /* From c78a41fc04f0209cba1e62ccbe6a4844633515e7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 15:28:18 +0200 Subject: [PATCH 0142/1268] ARM: s3c24xx: convert to sparse-irq As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 ++ arch/arm/mach-s3c/bast-ide.c | 2 +- arch/arm/mach-s3c/bast-irq.c | 2 +- arch/arm/mach-s3c/dev-audio-s3c64xx.c | 2 +- arch/arm/mach-s3c/dev-uart-s3c64xx.c | 2 +- arch/arm/mach-s3c/devs.c | 2 +- arch/arm/mach-s3c/gpio-samsung.c | 2 +- arch/arm/mach-s3c/irq-s3c24xx.c | 2 +- .../mach-s3c/{include/mach => }/irqs-s3c24xx.h | 18 ++++++++++++------ .../mach-s3c/{include/mach => }/irqs-s3c64xx.h | 0 arch/arm/mach-s3c/{include/mach => }/irqs.h | 0 arch/arm/mach-s3c/mach-amlm5900.c | 2 ++ arch/arm/mach-s3c/mach-anubis.c | 1 + arch/arm/mach-s3c/mach-anw6410.c | 2 +- arch/arm/mach-s3c/mach-at2440evb.c | 1 + arch/arm/mach-s3c/mach-bast.c | 1 + arch/arm/mach-s3c/mach-crag6410-module.c | 2 +- arch/arm/mach-s3c/mach-crag6410.c | 2 +- arch/arm/mach-s3c/mach-gta02.c | 1 + arch/arm/mach-s3c/mach-h1940.c | 1 + arch/arm/mach-s3c/mach-hmt.c | 2 +- arch/arm/mach-s3c/mach-jive.c | 2 +- arch/arm/mach-s3c/mach-mini2440.c | 3 ++- arch/arm/mach-s3c/mach-mini6410.c | 2 +- arch/arm/mach-s3c/mach-n30.c | 2 ++ arch/arm/mach-s3c/mach-ncp.c | 2 +- arch/arm/mach-s3c/mach-nexcoder.c | 1 + arch/arm/mach-s3c/mach-osiris.c | 1 + arch/arm/mach-s3c/mach-otom.c | 1 + arch/arm/mach-s3c/mach-qt2410.c | 1 + arch/arm/mach-s3c/mach-real6410.c | 2 +- arch/arm/mach-s3c/mach-rx1950.c | 1 + arch/arm/mach-s3c/mach-rx3715.c | 1 + arch/arm/mach-s3c/mach-smartq5.c | 2 +- arch/arm/mach-s3c/mach-smartq7.c | 2 +- arch/arm/mach-s3c/mach-smdk2410.c | 1 + arch/arm/mach-s3c/mach-smdk2413.c | 3 +++ arch/arm/mach-s3c/mach-smdk2416.c | 1 + arch/arm/mach-s3c/mach-smdk2440.c | 1 + arch/arm/mach-s3c/mach-smdk2443.c | 2 +- arch/arm/mach-s3c/mach-smdk6400.c | 2 +- arch/arm/mach-s3c/mach-smdk6410.c | 2 +- arch/arm/mach-s3c/mach-tct_hammer.c | 1 + arch/arm/mach-s3c/mach-vr1000.c | 1 + arch/arm/mach-s3c/mach-vstms.c | 1 + arch/arm/mach-s3c/pl080.c | 2 +- arch/arm/mach-s3c/pm-core-s3c24xx.h | 2 +- arch/arm/mach-s3c/pm-s3c2412.c | 2 +- arch/arm/mach-s3c/pm-s3c64xx.c | 2 +- arch/arm/mach-s3c/pm.c | 2 +- arch/arm/mach-s3c/s3c2443.c | 2 +- arch/arm/mach-s3c/s3c24xx.h | 2 +- arch/arm/mach-s3c/s3c64xx.c | 2 +- arch/arm/mach-s3c/simtec-usb.c | 2 +- 54 files changed, 69 insertions(+), 36 deletions(-) rename arch/arm/mach-s3c/{include/mach => }/irqs-s3c24xx.h (95%) rename arch/arm/mach-s3c/{include/mach => }/irqs-s3c64xx.h (100%) rename arch/arm/mach-s3c/{include/mach => }/irqs.h (100%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2242d2ae8854..c06e008c90ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,8 +444,10 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GPIO_SAMSUNG select GPIOLIB + select IRQ_DOMAIN select S3C2410_WATCHDOG select SAMSUNG_ATAGS + select SPARSE_IRQ select USE_OF select WATCHDOG help diff --git a/arch/arm/mach-s3c/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c index da64db1811d8..67f0adc1fec0 100644 --- a/arch/arm/mach-s3c/bast-ide.c +++ b/arch/arm/mach-s3c/bast-ide.c @@ -20,7 +20,7 @@ #include #include "map.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c index d299f124e6dc..cfc2ddc65513 100644 --- a/arch/arm/mach-s3c/bast-irq.c +++ b/arch/arm/mach-s3c/bast-irq.c @@ -16,7 +16,7 @@ #include #include "regs-irq.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/dev-audio-s3c64xx.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c index fc2f077afd24..909e82c148ba 100644 --- a/arch/arm/mach-s3c/dev-audio-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c @@ -10,7 +10,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/dev-uart-s3c64xx.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c index 8288e8d6c092..f9c947b8971b 100644 --- a/arch/arm/mach-s3c/dev-uart-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c @@ -16,7 +16,7 @@ #include #include #include "map.h" -#include +#include "irqs.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/devs.c b/arch/arm/mach-s3c/devs.c index 1e266fc24f9b..9ac07c023adf 100644 --- a/arch/arm/mach-s3c/devs.c +++ b/arch/arm/mach-s3c/devs.c @@ -38,7 +38,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "gpio-samsung.h" #include "gpio-cfg.h" diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index fda2c01f5a08..b7fc7c41309c 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -26,7 +26,7 @@ #include -#include +#include "irqs.h" #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3776d5206f9b..088cc04b7431 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -26,7 +26,7 @@ #include #include -#include +#include "irqs.h" #include "regs-irq.h" #include "regs-gpio.h" diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h b/arch/arm/mach-s3c/irqs-s3c24xx.h similarity index 95% rename from arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h rename to arch/arm/mach-s3c/irqs-s3c24xx.h index aaf3bae08b52..fecbf7e440c6 100644 --- a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h +++ b/arch/arm/mach-s3c/irqs-s3c24xx.h @@ -108,6 +108,8 @@ #define IRQ_TC S3C2410_IRQSUB(9) #define IRQ_ADC S3C2410_IRQSUB(10) +#define NR_IRQS_S3C2410 (S3C2410_IRQSUB(10) + 1) + /* extra irqs for s3c2412 */ #define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) @@ -115,6 +117,7 @@ #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) +#define NR_IRQS_S3C2412 (S3C2410_IRQSUB(14) + 1) #define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) #define IRQ_S3C2416_DMA S3C2410_IRQ(17) @@ -146,13 +149,20 @@ #define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) #define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) -/* extra irqs for s3c2440 */ +#define NR_IRQS_S3C2416 (S3C2416_IRQ(7) + 1) + +/* extra irqs for s3c2440/s3c2442 */ #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ + +#define NR_IRQS_S3C2442 (S3C2410_IRQSUB(12) + 1) + #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) +#define NR_IRQS_S3C2440 (S3C2410_IRQSUB(14) + 1) + /* irqs for s3c2443 */ #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ @@ -186,11 +196,7 @@ #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) -#if defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2416_I2S1 + 1) -#else -#define NR_IRQS (IRQ_S3C2443_AC97 + 1) -#endif +#define NR_IRQS_S3C2443 (S3C2410_IRQSUB(28) + 1) /* compatibility define. */ #define IRQ_UART3 IRQ_S3C2443_UART3 diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h b/arch/arm/mach-s3c/irqs-s3c64xx.h similarity index 100% rename from arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h rename to arch/arm/mach-s3c/irqs-s3c64xx.h diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/irqs.h similarity index 100% rename from arch/arm/mach-s3c/include/mach/irqs.h rename to arch/arm/mach-s3c/irqs.h diff --git a/arch/arm/mach-s3c/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c index 94c4512ace17..f85e5885e9b4 100644 --- a/arch/arm/mach-s3c/mach-amlm5900.c +++ b/arch/arm/mach-s3c/mach-amlm5900.c @@ -239,7 +239,9 @@ static void __init amlm5900_init(void) MACHINE_START(AML_M5900, "AML_M5900") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = amlm5900_map_io, + .nr_irqs = NR_IRQS_S3C2410, .init_irq = s3c2410_init_irq, .init_machine = amlm5900_init, .init_time = amlm5900_init_time, diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 60df40052209..4536f3e66e27 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -414,6 +414,7 @@ static void __init anubis_init(void) MACHINE_START(ANUBIS, "Simtec-Anubis") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c index 825714e9ac66..b67eae43e04f 100644 --- a/arch/arm/mach-s3c/mach-anw6410.c +++ b/arch/arm/mach-s3c/mach-anw6410.c @@ -40,7 +40,7 @@ #include "devs.h" #include "cpu.h" -#include +#include "irqs.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index c6a5a51d84aa..743403d873e0 100644 --- a/arch/arm/mach-s3c/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -225,6 +225,7 @@ static void __init at2440evb_init(void) MACHINE_START(AT2440EVB, "AT2440EVB") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 5ac24e406157..a33ceab81e09 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -575,6 +575,7 @@ static void __init bast_init(void) MACHINE_START(BAST, "Simtec-BAST") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = bast_map_io, .init_irq = s3c2410_init_irq, .init_machine = bast_init, diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 5d1d4b67a4b7..4edde13b89b5 100644 --- a/arch/arm/mach-s3c/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -28,7 +28,7 @@ #include #include "cpu.h" -#include +#include "irqs.h" #include "crag6410.h" diff --git a/arch/arm/mach-s3c/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c index e3e0fe897bcc..9a45474d1bf7 100644 --- a/arch/arm/mach-s3c/mach-crag6410.c +++ b/arch/arm/mach-s3c/mach-crag6410.c @@ -47,7 +47,7 @@ #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" -#include +#include "irqs.h" #include "fb.h" #include "sdhci.h" diff --git a/arch/arm/mach-s3c/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c index 418939ce0fc3..abfdce765525 100644 --- a/arch/arm/mach-s3c/mach-gta02.c +++ b/arch/arm/mach-s3c/mach-gta02.c @@ -572,6 +572,7 @@ static void __init gta02_init_time(void) MACHINE_START(NEO1973_GTA02, "GTA02") /* Maintainer: Nelson Castillo */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2442, .map_io = gta02_map_io, .init_irq = s3c2442_init_irq, .init_machine = gta02_machine_init, diff --git a/arch/arm/mach-s3c/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c index 8a43ed1c4c4d..032b18837855 100644 --- a/arch/arm/mach-s3c/mach-h1940.c +++ b/arch/arm/mach-s3c/mach-h1940.c @@ -793,6 +793,7 @@ static void __init h1940_init(void) MACHINE_START(H1940, "IPAQ-H1940") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = h1940_map_io, .reserve = h1940_reserve, .init_irq = s3c2410_init_irq, diff --git a/arch/arm/mach-s3c/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c index b287e9987311..49ba16c447aa 100644 --- a/arch/arm/mach-s3c/mach-hmt.c +++ b/arch/arm/mach-s3c/mach-hmt.c @@ -26,7 +26,7 @@ #include