diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1/Makefile b/arch/arm64/boot/dts/rockchip/overlays/odroidm1/Makefile index 7c0cf0aa8b3d..94e5a241be5e 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/odroidm1/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1/Makefile @@ -5,6 +5,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += \ can0.dtbo \ dht11.dtbo \ display_vu8m.dtbo \ + fiq0_to_uart2.dtbo \ hktft32.dtbo \ i2c0.dtbo \ i2c1.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1/fiq0_to_uart2.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1/fiq0_to_uart2.dts new file mode 100644 index 000000000000..b9c87c82aaa5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1/fiq0_to_uart2.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/{ + fragment@0 { + target = <&fiq_debugger>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile index 214e29954c85..9e48f2764ed3 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/Makefile @@ -7,6 +7,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += \ display_3_5.dtbo \ display_5_0.dtbo \ display_vu8s.dtbo \ + fiq0_to_uart2.dtbo \ hktft32.dtbo \ i2c0.dtbo \ i2c1.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/fiq0_to_uart2.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/fiq0_to_uart2.dts new file mode 100644 index 000000000000..b9c87c82aaa5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm1s/fiq0_to_uart2.dts @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/{ + fragment@0 { + target = <&fiq_debugger>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@1 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + }; + }; +};