From 11ca1d9953b94a430010093d432dfb1a1776bbc5 Mon Sep 17 00:00:00 2001 From: William Wu Date: Mon, 21 Oct 2024 18:19:42 +0800 Subject: [PATCH 1/4] phy: rockchip: usbdp: Fix LFPS detect threshold control According to the LFPS Tx Low Power/LFPS Rx Detect Threshold [1], the device under test(DUT) must not respond if LFPS below the minimum LFPS Rx Detect Threshold 100mV. Test fail on Rockchip platforms, because the default LFPS detect threshold is set to 65mV. The usbdp phy LFPS detect threshold voltage could be set to 30mV ~ 140mV, and since there could be 10-20% PVT variation, we set LFPS detect threshold voltage to 110mV. [1] https://compliance.usb.org/resources/LFPS_Rx_Tx_Low_Power_Compliance_Update_Rev5.pdf Change-Id: Idf17df242090027b3b8eb731423a1aa536ed8c09 Signed-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 520059604da1..d5f8e18022d9 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -401,7 +401,8 @@ static const struct reg_sequence udphy_init_sequence[] = { {0x0070, 0x7D}, {0x0074, 0x68}, {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, {0x0440, 0x3F}, {0x10D4, 0x08}, - {0x20D4, 0x08}, {0x0024, 0x6e} + {0x20D4, 0x08}, {0x0024, 0x6e}, + {0x09C0, 0x0A}, {0x19C0, 0x0A} }; static inline int grfreg_write(struct regmap *base, From 87c6fc5b1eb6f3109d8488e1da666adccc67b8bb Mon Sep 17 00:00:00 2001 From: Jianlong Wang Date: Tue, 22 Oct 2024 11:37:08 +0800 Subject: [PATCH 2/4] net: rfkill: rfkill-wlan: fix compilation error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit implicit declaration of function ‘random_ether_addr’ Change-Id: Ibf8c391b43f25b638062686a5e4f396bf79223f0 Signed-off-by: Jianlong Wang --- net/rfkill/rfkill-wlan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/rfkill/rfkill-wlan.c b/net/rfkill/rfkill-wlan.c index 030ec518db0c..7cd3b242211c 100644 --- a/net/rfkill/rfkill-wlan.c +++ b/net/rfkill/rfkill-wlan.c @@ -434,7 +434,7 @@ static int get_wifi_addr_vendor(unsigned char *addr) LOG("%s: rk_vendor_read wifi mac address failed (%d)\n", __func__, ret); #ifdef CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR - random_ether_addr(addr); + eth_random_addr(addr); LOG("%s: generate random wifi mac address: " "%02x:%02x:%02x:%02x:%02x:%02x\n", __func__, addr[0], addr[1], addr[2], addr[3], addr[4], From a921bd7a8fca3e6c2ebcc39dec24b8d1e2573a69 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Wed, 18 Sep 2024 11:36:20 +0800 Subject: [PATCH 3/4] memory: dsmc: fix bug in multi cs and region Change-Id: I792667c6a4a7e9f120da29b1fef19cbd2b40ed9e Signed-off-by: Zhihuan He --- drivers/memory/rockchip/dsmc-controller.c | 8 ++++++-- drivers/memory/rockchip/dsmc-host.c | 1 + drivers/memory/rockchip/dsmc-host.h | 4 ++-- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/memory/rockchip/dsmc-controller.c b/drivers/memory/rockchip/dsmc-controller.c index 30b836772dfb..d4e85f85cdc9 100644 --- a/drivers/memory/rockchip/dsmc-controller.c +++ b/drivers/memory/rockchip/dsmc-controller.c @@ -295,8 +295,12 @@ static int dsmc_ctrller_cfg_for_lb(struct rockchip_dsmc *dsmc, uint32_t cs) dsmc->regs + DSMC_RGN0_ATTR(cs) + 4 * i); } /* clear and enable interrupt */ - writel(INT_STATUS(cfg->int_en), dsmc->regs + DSMC_INT_STATUS); - writel(INT_EN(cfg->int_en), dsmc->regs + DSMC_INT_EN); + REG_CLRSETBITS(dsmc, DSMC_INT_STATUS, + INT_STATUS_MASK(cfg->int_en), + INT_STATUS(cfg->int_en)); + REG_CLRSETBITS(dsmc, DSMC_INT_EN, + INT_EN_MASK(cfg->int_en), + INT_EN(cfg->int_en)); if (dsmc->cfg.dma_req_mux_offset && (cs < 2)) REG_CLRSETBITS(dsmc, dsmc->cfg.dma_req_mux_offset, diff --git a/drivers/memory/rockchip/dsmc-host.c b/drivers/memory/rockchip/dsmc-host.c index e0ad14ab2dfc..b96e012d395d 100644 --- a/drivers/memory/rockchip/dsmc-host.c +++ b/drivers/memory/rockchip/dsmc-host.c @@ -278,6 +278,7 @@ static int dsmc_reg_remap(struct device *dev, struct dsmc_ctrl_config *cfg, region_map->size, DSMC_MEM_ATTRIBUTE_NO_CACHE); } else if (cfg->cs_cfg[cs].device_type == DSMC_LB_DEVICE) { + num = 0; for (rgn = 0; rgn < DSMC_LB_MAX_RGN; rgn++) { if (!cfg->cs_cfg[cs].slv_rgn[rgn].status) continue; diff --git a/drivers/memory/rockchip/dsmc-host.h b/drivers/memory/rockchip/dsmc-host.h index f51bf5763460..9e4f7671a594 100644 --- a/drivers/memory/rockchip/dsmc-host.h +++ b/drivers/memory/rockchip/dsmc-host.h @@ -58,12 +58,12 @@ /* INT_EN */ #define INT_EN_SHIFT 0 -#define INT_EN_MASK 0xf +#define INT_EN_MASK(cs) (0x1 << (cs)) #define INT_EN(cs) (0x1 << (cs)) /* INT_STATUS */ #define INT_STATUS_SHIFT 0 -#define INT_STATUS_MASK 0xf +#define INT_STATUS_MASK(cs) (0x1 << (cs)) #define INT_STATUS(cs) (0x1 << (cs)) /* INT_MASK */ From fc59a282e70cd4ab12cc1ec7ebc1e9e442a351f7 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 21 Oct 2024 15:45:03 +0800 Subject: [PATCH 4/4] PCI: rockchip: dw: Add rockchip,wait-for-link-ms support Some devices like FPGA or AI cards need a long period of time after powering up and releasing #PERST. This is due to the slow firmware loading process happened inside the devices. Without this support, link will be failed during the limitation. Signed-off-by: Shawn Lin Change-Id: I01ecb64ca1b1a1917eb5434c374517387ab11ffc --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index af1155b388c8..238a58053c9c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -127,6 +127,7 @@ struct rk_pcie { struct gpio_desc *rst_gpio; u32 perst_inactive_ms; u32 s2r_perst_inactive_ms; + u32 wait_for_link_ms; struct gpio_desc *prsnt_gpio; struct dma_trx_obj *dma_obj; bool in_suspend; @@ -398,12 +399,14 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1); /* - * Add this 1ms delay because we observe link is always up stably after it and - * could help us save 20ms for scanning devices. + * Add this delay because we observe devices need a period of time to be able to + * work, so the link is always up stably after it. And the default 1ms could help us + * save 20ms for scanning devices. If the devices need longer than 2s to be able to + * work, please change wait_for_link_ms via dts. */ usleep_range(1000, 1100); - for (retries = 0; retries < 100; retries++) { + for (retries = 0; retries < rk_pcie->wait_for_link_ms / 20; retries++) { if (dw_pcie_link_up(pci)) { /* * We may be here in case of L0 in Gen1. But if EP is capable @@ -427,7 +430,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci) dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); rk_pcie_debug_dump(rk_pcie); - msleep(20); + usleep_range(20000, 21000); } /* @@ -682,6 +685,10 @@ static int rk_pcie_resource_get(struct platform_device *pdev, &rk_pcie->s2r_perst_inactive_ms)) rk_pcie->s2r_perst_inactive_ms = rk_pcie->perst_inactive_ms; + device_property_read_u32(&pdev->dev, "rockchip,wait-for-link-ms", + &rk_pcie->wait_for_link_ms); + rk_pcie->wait_for_link_ms = max_t(u32, rk_pcie->wait_for_link_ms, 2000); + rk_pcie->prsnt_gpio = devm_gpiod_get_optional(&pdev->dev, "prsnt", GPIOD_IN); if (IS_ERR_OR_NULL(rk_pcie->prsnt_gpio)) dev_info(&pdev->dev, "invalid prsnt-gpios property in node\n");