From bd22b8ce75157ef4453fbae160f50d20a7c99297 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Tue, 29 Dec 2020 16:13:02 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: Make some changes for scmi 1. Use DDR 1M+60K~1M+64K instead of sram to be share memory. 2. Delete property "shmem" in scmi_clk node. 3. Change smc-id to 0x82000010. Change-Id: I97f25dec6b61fb749b1ef79ef9875abe48fa662e Signed-off-by: XiaoDong Huang --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index a2f46dfc4d3a..6da9ab15bed0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -226,13 +226,12 @@ scmi: scmi { compatible = "arm,scmi-smc"; shmem = <&scmi_shmem>; - arm,smc-id = <0x8200000f>; + arm,smc-id = <0x82000010>; #address-cells = <1>; #size-cells = <0>; scmi_clk: protocol@14 { reg = <0x14>; - shmem = <&scmi_shmem>; #clock-cells = <1>; }; }; @@ -346,6 +345,11 @@ pinctrl-0 = <&clk32k_out0>; }; + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + sata0: sata@fc000000 { compatible = "snps,dwc-ahci"; reg = <0 0xfc000000 0 0x1000>; @@ -667,11 +671,6 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0xfdcc0000 0xc000>; - - scmi_shmem: scmi-shmem@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; - }; }; pmucru: clock-controller@fdd00000 {