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phy: rockchip-inno-usb2: add usb-phy support for rk3308

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This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.

Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This commit is contained in:
Frank Wang
2018-03-05 11:44:20 +08:00
committed by Tao Huang
parent e6f2f6d63e
commit bdeb719242
2 changed files with 56 additions and 0 deletions
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2
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
View File

@@ -5,6 +5,7 @@ Required properties (phy (parent) node):
* "rockchip,px30-usb2phy"
* "rockchip,rk3128-usb2phy"
* "rockchip,rk322x-usb2phy"
* "rockchip,rk3308-usb2phy"
* "rockchip,rk3328-usb2phy"
* "rockchip,rk3366-usb2phy"
* "rockchip,rk3368-usb2phy"
@@ -86,6 +87,7 @@ grf: syscon@ff770000 {
Required properties (usb2phy grf node):
- compatible : should be one of the listed compatibles:
"rockchip,px30-usb2phy-grf", "syscon", "simple-mfd";
"rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
"rockchip,rk3328-usb2phy-grf", "syscon", "simple-mfd";
- reg : the address offset of grf for usb-phy configuration.
- #address-cells : should be 1.

54
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View File

@@ -2157,6 +2157,59 @@ static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
{
.reg = 0x100,
.num_ports = 2,
.clkout_ctl = { 0x0108, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
.bvalid_det_en = { 0x3020, 2, 2, 0, 1 },
.bvalid_det_st = { 0x3024, 2, 2, 0, 1 },
.bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
.iddig_output = { 0x0100, 10, 10, 0, 1 },
.iddig_en = { 0x0100, 9, 9, 0, 1 },
.idfall_det_en = { 0x3020, 5, 5, 0, 1 },
.idfall_det_st = { 0x3024, 5, 5, 0, 1 },
.idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
.idrise_det_en = { 0x3020, 4, 4, 0, 1 },
.idrise_det_st = { 0x3024, 4, 4, 0, 1 },
.idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
.ls_det_en = { 0x3020, 0, 0, 0, 1 },
.ls_det_st = { 0x3024, 0, 0, 0, 1 },
.ls_det_clr = { 0x3028, 0, 0, 0, 1 },
.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
.utmi_iddig = { 0x0120, 6, 6, 0, 1 },
.utmi_ls = { 0x0120, 5, 4, 0, 1 },
.vbus_det_en = { 0x001c, 15, 15, 1, 0 },
},
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
.ls_det_en = { 0x3020, 1, 1, 0, 1 },
.ls_det_st = { 0x3024, 1, 1, 0, 1 },
.ls_det_clr = { 0x3028, 1, 1, 0, 1 },
.utmi_ls = { 0x120, 17, 16, 0, 1 },
.utmi_hstdet = { 0x120, 19, 19, 0, 1 }
}
},
.chg_det = {
.opmode = { 0x0100, 3, 0, 5, 1 },
.cp_det = { 0x0120, 24, 24, 0, 1 },
.dcp_det = { 0x0120, 23, 23, 0, 1 },
.dp_det = { 0x0120, 25, 25, 0, 1 },
.idm_sink_en = { 0x0108, 8, 8, 0, 1 },
.idp_sink_en = { 0x0108, 7, 7, 0, 1 },
.idp_src_en = { 0x0108, 9, 9, 0, 1 },
.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
},
},
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
{
.reg = 0x100,
@@ -2353,6 +2406,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs },
{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
{ .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },