From 02ee7a133ecb4c371d9fbcf3461840cb42bcc43a Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 9 Aug 2023 16:57:47 +0800 Subject: [PATCH] PCIe: dw: rockchip: rework compliance test settings There are three types of compliance mode test requirement right now, consolidate them together: [1] SMA tool: rockchip,compliance-mode = <0 ANY_VALUE_FROM_0_TO_10>; [2] Soldered board: rockchip,compliance-mode = ; mode: 1->Gen1 2->Gen2 3->Gen3 preset: 0->p0 1->p1 2->p2 .... etc. [3] lookback: same as SMA tool case Signed-off-by: Shawn Lin Change-Id: I180b4881d827e3c2f0fc22f0bab4ca165be44c19 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 25 +++++++++++++++---- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 760171b70bd4..f44003c6cabb 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -192,6 +192,7 @@ struct rk_pcie { u32 msi_vector_num; struct workqueue_struct *hot_rst_wq; struct work_struct hot_rst_work; + u32 comp_prst[2]; }; struct rk_pcie_of_data { @@ -2081,11 +2082,25 @@ retry_regulator: rk_pcie->is_signal_test = true; } - /* Force into compliance mode */ - if (device_property_read_bool(dev, "rockchip,compliance-mode")) { - val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); - val |= BIT(4); - dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); + /* + * Force into compliance mode + * comp_prst is a two dimensional array of which the first element + * stands for speed mode, and the second one is preset value encoding: + * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting + * [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero. + */ + if (device_property_read_u32_array(dev, "rockchip,compliance-mode", + rk_pcie->comp_prst, 2)) { + BUG_ON(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10); + if (!rk_pcie->comp_prst[0]) { + dev_info(dev, "Auto compliance mode for SMA tool.\n"); + } else { + dev_info(dev, "compliance mode for soldered board Gen%d, P%d.\n", + rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]); + val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); + val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12); + dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); + } rk_pcie->is_signal_test = true; }