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media: hdmitx: Update hdmi hpll generation logic of custombuilt mode

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Change-Id: If4ab95d0c95ac49f4ce78801e1c2346e6301635e
This commit is contained in:
Joy Cho
2019-06-17 14:51:49 +09:00
parent ec76d12c6a
commit be56805ce4
1 changed files with 6 additions and 2 deletions
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8
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
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@@ -1043,8 +1043,8 @@ next:
p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10);
pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n",
__func__, custom_timing->frac_freq);
/* check if hpll clk output is under (100*10)MHz */
if (p_enc[j].hpll_clk_out < 1000000) {
/* check if hpll clk output is under (140*10)MHz */
if (p_enc[j].hpll_clk_out < 1400000) {
p_enc[j].hpll_clk_out *= 4;
/* control od dividers */
p_enc[j].od1 = 4;
@@ -1056,6 +1056,10 @@ next:
p_enc[j].od2 = 1;
p_enc[j].od3 = 2;
}
pr_info("[N2] hpll_clk_out %d, od1 %d, od2 %d, od3 %d\n",
p_enc[j].hpll_clk_out,
p_enc[j].od1, p_enc[j].od2, p_enc[j].od3);
}
hdmitx_set_cts_sys_clk(hdev);