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ARM64: dts: rk3366: assign rates for aclk_bus and aclk_peri
Assign rates for aclk_bus and aclk_peri according to our original design. Change-Id: Iab4961d485421151be5dbdacf6929800150ab342 Signed-off-by: Feng Xiao <xf@rock-chips.com>
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@@ -668,7 +668,9 @@
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<&cru PLL_NPLL>, <&cru PLL_MPLL>,
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<&cru PLL_WPLL>, <&cru PLL_BPLL>,
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<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
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<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
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<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
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<&cru ACLK_BUS>, <&cru ACLK_PERI0>,
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<&cru ACLK_PERI1>;
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assigned-clock-rates =
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<0>,
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<0>, <0>,
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@@ -676,7 +678,9 @@
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<594000000>, <594000000>,
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<960000000>, <520000000>,
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<375000000>, <288000000>,
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<100000000>, <100000000>;
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<100000000>, <100000000>,
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<288000000>, <288000000>,
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<144000000>;
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assigned-clock-parents =
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<&cru SCLK_32K_INTR>,
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<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
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