From bf586a6af75c715796f9c17a02cd448ec9b1737d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 27 Mar 2018 15:18:23 +0800 Subject: [PATCH] clk: rockchip: rk3308: Change pll type to pll_rk3328 The clk_rtc32k is unused for pll on rk3308 and it will increase the time to change armclk rate. Change-Id: I4c1afd04693dafb97c5119de012884c997f596ae Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3308.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 9c6c447a585f..b18d6bfeb869 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -126,7 +126,7 @@ static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = { .mux_core_mask = 0x3, }; -PNAME(mux_pll_p) = { "xin24m", "clk_rtc32k" }; +PNAME(mux_pll_p) = { "xin24m" }; PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" }; PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" }; PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" }; @@ -184,16 +184,16 @@ PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" }; PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" }; static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = { - [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3308_PLL_CON(0), RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates), - [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3308_PLL_CON(8), RK3308_MODE_CON, 2, 1, 0, NULL), - [vpll0] = PLL(pll_rk3036, PLL_VPLL0, "vpll0", mux_pll_p, + [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 0, RK3308_PLL_CON(16), RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates), - [vpll1] = PLL(pll_rk3036, PLL_VPLL1, "vpll1", mux_pll_p, + [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, 0, RK3308_PLL_CON(24), RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates), };