From bf69e15bdc35497c30295514af5f0bcee5d574ba Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 19 Mar 2025 15:22:14 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Set rk3562 gate_tx_pck_sel length select work for L1SS Change-Id: I18a163b70d9387a9b8b9ca2cb24dc95780592761 Signed-off-by: Jon Lin --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 4cc8ecaed250..723e7856232b 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -707,6 +707,9 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) case 100000000: rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->mode == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ + rockchip_combphy_updatel(priv, GENMASK(7, 7), BIT(7), 0x1d << 2); + /* PLL KVCO tuning fine */ rockchip_combphy_updatel(priv, GENMASK(4, 2), 0x2 << 2, 0x20 << 2);