From bf77a65fee6430723d7e3f54ffd60f356cb441ea Mon Sep 17 00:00:00 2001
From: Zou Dengming <marsow.zou@rock-chips.com>
Date: Tue, 9 Mar 2021 15:13:12 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3566-box-demo-v10: enable mipi camera
 gc4c33 or gc8034

Change-Id: Id3b8a317f0018d6a044bf95f3e58967ee5113741
Signed-off-by: Zou Dengming <marsow.zou@rock-chips.com>
---
 .../dts/rockchip/rk3566-box-demo-v10.dtsi     | 136 ++++++++++++++++++
 1 file changed, 136 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
index 58fb6548ed9e..7672960957cf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
@@ -87,6 +87,17 @@
 		regulator-always-on;
 	};
 
+	vcc_camera: vcc-camera-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&camera_pwr>;
+		regulator-name = "vcc_camera";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	wireless_wlan: wireless-wlan {
 		compatible = "wlan-platdata";
 		rockchip,grf = <&grf>;
@@ -125,6 +136,47 @@
 	status = "okay";
 };
 
+&csi2_dphy_hw {
+	status = "okay";
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in_ucam0: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&gc4c33_out>;
+				data-lanes = <1 2>;
+			};
+
+			mipi_in_ucam1: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&gc8034_out>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&isp0_in>;
+			};
+		};
+	};
+};
+
 &gmac1 {
 	phy-mode = "rgmii";
 	clock_in_out = "input";
@@ -152,6 +204,60 @@
 	status = "okay";
 };
 
+&i2c2{
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2m1_xfer>;
+
+	gc8034: gc8034@37 {
+		status = "okay";
+		compatible = "galaxycore,gc8034";
+		reg = <0x37>;
+		clocks = <&cru CLK_CIF_OUT>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3568_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clk>;
+		/*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
+		rockchip,camera-module-lens-name = "CK8401";
+		port {
+			gc8034_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+
+	gc4c33: gc4c33@29 {
+		status = "okay";
+		compatible = "galaxycore,gc4c33";
+		reg = <0x29>;
+		clocks = <&cru CLK_CIF_OUT>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3568_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clk>;
+		/*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "PCORW0009A";
+		rockchip,camera-module-lens-name = "40IRC-4M";
+		port {
+			gc4c33_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
 &mdio1 {
 	rgmii_phy1: phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -277,6 +383,28 @@
 	vccio7-supply = <&vcc_3v3>;
 };
 
+&rkisp {
+	status = "okay";
+};
+
+&rkisp_mmu {
+	status = "okay";
+};
+
+&rkisp_vir0 {
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp0_in: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&csidphy_out>;
+		};
+	};
+};
+
 &sdmmc0 {
 	max-frequency = <50000000>;
 	supports-sd;
@@ -335,6 +463,14 @@
 };
 
 &pinctrl {
+	cam {
+		camera_pwr: camera-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sdio-pwrseq {
 		wifi_enable_h: wifi-enable-h {
 			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;