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vpp: sr: remove the vpp misc operation in sr function [1/1]

Browse Source 
PD#SWPL-2613

Problem:
sr mux in vpp misc is set incorrectly.

Solution:
move the vpp misc operation together

Verify:
verify by x301

Change-Id: Ie813e5b04b97a4481c2e45bcf0c8b4c065fb9f69
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-12-03 22:04:24 +08:00
committed by Luke Go
parent fe2b605225
commit c00bcbfa05
4 changed files with 100 additions and 29 deletions
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4
include/linux/amlogic/media/video_sink/video.h
View File

@@ -99,7 +99,11 @@ enum {
#define VPP_POST_FG_SEL_MASK (1 << 4)
#define VPP_POST_FG_OSD2 (1 << 4)
#define VPP_POST_FG_OSD1 (0 << 4)
#define DNLP_SR1_CM (1 << 3)
#define SR1_AFTER_POSTBLEN (0 << 3)
#define VPP_FIFO_RESET_DE (1 << 2)
#define PREBLD_SR0_VD1_SCALER (1 << 1)
#define SR0_AFTER_DNLP (0 << 1)
#define VPP_OUT_SATURATE (1 << 0)
#define VDIF_RESET_ON_GO_FIELD (1<<29)

4
include/linux/amlogic/media/video_sink/vpp.h
View File

@@ -151,6 +151,9 @@ struct vpp_frame_par_s {
bool nocomp;
u8 sr0_position;
u8 sr1_position;
u8 sr_core_support;
};
struct disp_info_s {
@@ -198,6 +201,7 @@ enum select_scaler_path_e {
/*tl1 have core0/core1, support below mode*/
PPS_CORE0_CORE1,
PPS_CORE0_POSTBLEND_CORE1,
CORE0_PPS_POSTBLEND_CORE1,
SCALER_PATH_MAX,
};
/*