From c02eb29f5184c08d340c0b45f2b6fc1d3ed73eb0 Mon Sep 17 00:00:00 2001
From: Luke Go <sangch.go@gmail.com>
Date: Thu, 26 Mar 2020 17:51:58 +0900
Subject: [PATCH] ODROID-COMMON: device-tree refactor

This patch is to define a common dtsi for ODROID boards, sm1 APs.

Change-Id: Id9f5ee8c96b2687e1205e2cb8898b9f934ef3f41
---
 .../boot/dts/amlogic/meson64_odroidc4.dts     | 79 ++++++++++---------
 .../dts/amlogic/mesonsm1_odroid_common.dtsi   | 27 +------
 2 files changed, 41 insertions(+), 65 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson64_odroidc4.dts b/arch/arm64/boot/dts/amlogic/meson64_odroidc4.dts
index e8146191a031..5de325a56f3e 100644
--- a/arch/arm64/boot/dts/amlogic/meson64_odroidc4.dts
+++ b/arch/arm64/boot/dts/amlogic/meson64_odroidc4.dts
@@ -29,6 +29,13 @@
 
 	chosen { };
 
+	gpiomem {
+		compatible = "amlogic, gpiomem";
+		reg = <0x0 0xff634000 0x0 0x1000>,	/* GPIO banks */
+			<0x0 0xff800000 0x0 0x1000>;	/* GPIO_AO bank*/
+		status = "okay";
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -49,12 +56,20 @@
 			alignment = <0x0 0x400000>;
 			alloc-ranges = <0x0 0x05000000 0x0 0x400000>;
 		};
+
 		secos_reserved:linux,secos {
 			status = "disable";
 			compatible = "amlogic, aml_secos_memory";
 			reg = <0x0 0x05300000 0x0 0x2000000>;
 			no-map;
 		};
+
+		/*  POST PROCESS MANAGER */
+		ppmgr_reserved:linux,ppmgr {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x0>;
+		};
+
 		logo_reserved:linux,meson-fb {
 			compatible = "shared-dma-pool";
 			reusable;
@@ -92,12 +107,6 @@
 			size = <0x0 0x02800000>;
 			alignment = <0x0 0x400000>;
 		};
-		/*  POST PROCESS MANAGER */
-		ppmgr_reserved:linux,ppmgr {
-			compatible = "shared-dma-pool";
-			size = <0x0 0x0>;
-		};
-
 		codec_mm_cma:linux,codec_mm_cma {
 			compatible = "shared-dma-pool";
 			reusable;
@@ -775,24 +784,6 @@
 	sd_vddio_gpio = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>;
 };
 
-&sd_emmc_c {
-	status = "okay";
-	emmc {
-		caps = "MMC_CAP_8_BIT_DATA",
-			 "MMC_CAP_MMC_HIGHSPEED",
-			 "MMC_CAP_SD_HIGHSPEED",
-			 "MMC_CAP_NONREMOVABLE",
-			/* "MMC_CAP_1_8V_DDR", */
-			 "MMC_CAP_HW_RESET",
-			 "MMC_CAP_ERASE",
-			 "MMC_CAP_CMD23";
-		caps2 = "MMC_CAP2_HS200";
-		/* "MMC_CAP2_HS400";*/
-		f_min = <400000>;
-		f_max = <200000000>;
-	};
-};
-
 &sd_emmc_b {
 	status = "okay";
 	sd-uhs-sdr25;
@@ -832,23 +823,33 @@
 	};
 };
 
-&sd_emmc_b2 {
-	status = "okay";
-	sd {
-		caps = "MMC_CAP_4_BIT_DATA",
-			"MMC_CAP_UHS_SDR50",
-			"MMC_CAP_UHS_SDR104",
-			"MMC_CAP_MMC_HIGHSPEED",
-			"MMC_CAP_SD_HIGHSPEED";
-		vol_switch = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
-		vol_switch_18 = <1>;
-		f_min = <400000>;
-		f_max = <100000000>;
+&pinctrl_periphs {
+	tdmout_a: tdmout_a {
+		mux { /* GPIOX_9, GPIOX_10, GPIOX_11 */
+			groups = "tdma_sclk",
+				"tdma_fs",
+				"tdma_dout0";
+			function = "tdma_out";
+			drive-strength = <2>;
+		};
 	};
 };
-&meson_cooldev {
-	status = "okay";
-};
+
+&pinctrl_aobus {
+	spdifout: spdifout {
+		mux {/* GPIOAO_10 */
+			groups = "spdif_out_ao";
+			function = "spdif_out_ao";
+		};
+	};
+	tdma_mclk: tdma_mclk {
+		mux {
+			groups = "mclk0_ao";
+			function = "mclk0_ao";
+			drive-strength = <2>;
+		};
+	};
+}; /* end of pinctrl_aobus */
 
 &spicc0 {
 	status = "disabled";
diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1_odroid_common.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1_odroid_common.dtsi
index c4a1346b9d6c..fbea3a3a52e4 100644
--- a/arch/arm64/boot/dts/amlogic/mesonsm1_odroid_common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonsm1_odroid_common.dtsi
@@ -33,12 +33,6 @@
 		spi1 = &spicc1;
 	};
 
-	gpiomem {
-		compatible = "amlogic, gpiomem";
-		reg = <0x0 0xff634000 0x0 0x1000>;
-		status = "okay";
-	};
-
 	codec_mm {
 		compatible = "amlogic, codec, mm";
 		memory-region = <&codec_mm_cma &codec_mm_reserved>;
@@ -107,13 +101,6 @@
 		gpios = <&gpio GPIOA_13 GPIO_ACTIVE_HIGH>;
 		status = "disabled";
 	};
-
-	pwmgpio:pwmgpio {
-		compatible = "pwm-gpio";
-		#pwm-cells = <3>;
-		pwm-gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
 };
 
 &ethmac {
@@ -177,11 +164,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_master_pins1>;
 	clock-frequency = <100000>;		/* default 100k */
-
-	pcf8563: rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-	};
 };
 
 &usb2_phy_v2 {
@@ -201,7 +183,7 @@
 
 &pcie_A {
 	reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>;
-	status = "disable";
+	status = "disabled";
 };
 
 &sd_emmc_c {
@@ -213,7 +195,6 @@
 			 "MMC_CAP_MMC_HIGHSPEED",
 			 "MMC_CAP_SD_HIGHSPEED",
 			 "MMC_CAP_NONREMOVABLE",
-			 "MMC_CAP_1_8V_DDR",
 			 "MMC_CAP_HW_RESET",
 			 "MMC_CAP_ERASE",
 			 "MMC_CAP_CMD23";
@@ -235,12 +216,6 @@
 			drive-strength = <3>;
 		};
 	};
-	spdifout: spdifout {
-		mux {/* GPIOA_11 */
-			groups = "spdif_out_a11";
-			function = "spdif_out";
-		};
-	};
 	pwmcd_to_gpios:pwmcd_gpio {
 		mux {
 			groups = "GPIOX_5", "GPIOX_6";