From c115ee06bc96c85a8dee9be9a1d2b2e8cc386487 Mon Sep 17 00:00:00 2001
From: Steven Liu <steven.liu@rock-chips.com>
Date: Mon, 6 Feb 2023 15:23:38 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3562-amp: add rpmsg node

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I4a1b1842414042c91a3365161f3baea236f7dc7d
---
 arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 28 ++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
index 80e194e2bcec..66ece0360c78 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
@@ -7,9 +7,11 @@
 	rockchip_amp: rockchip-amp {
 		compatible = "rockchip,mcu-amp";
 		clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>,
+			<&cru PCLK_MAILBOX>, <&cru PCLK_INTC>,
 			<&cru SCLK_UART5>, <&cru PCLK_UART5>,
 			<&cru PCLK_TIMER>, <&cru CLK_TIMER5>;
 		clock-names = "fclk_bus_cm0_core", "clk_bus_cm0_rtc",
+			      "pclk_maikbox", "pclk_intc",
 			      "baudclk", "apb_pclk", "pclk", "timer";
 
 		pinctrl-names = "default";
@@ -18,6 +20,18 @@
 		status = "okay";
 	};
 
+	rpmsg: rpmsg@a0000000 {
+		compatible = "rockchip,rk3562-rpmsg";
+		mbox-names = "rpmsg-rx", "rpmsg-tx";
+		mboxes = <&mailbox 0 &mailbox 3>;
+		rockchip,vdev-nums = <1>;
+		rockchip,link-id = <0x04>;
+		reg = <0x0 0xa0000000 0x0 0x20000>;
+		memory-region = <&rpmsg_dma_reserved>;
+
+		status = "okay";
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -28,6 +42,20 @@
 			reg = <0x0 0x8200000 0x0 0x100000>;
 			no-map;
 		};
+
+		rpmsg_reserved: rpmsg@a0000000 {
+			reg = <0x0 0xa0000000 0x0 0x400000>;
+			no-map;
+		};
+
+		rpmsg_dma_reserved: rpmsg-dma@a0400000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xa0400000 0x0 0x100000>;
+			no-map;
+		};
 	};
 };
 
+&mailbox {
+	status = "okay";
+};