From c18fd2aea2efff6cabf9b8524d693d9832f6b441 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 3 Sep 2021 08:27:21 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: Set SDHCI core clk to 200MHz As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, host->max_clk is derived from core clock in the first place. Then f_max works together with it. If we adjust loader's core clk setting, such as 50MHz, we will get 50MHz for host->max_clk, because .get_max_clock() reads core clk when probing driver. That will lead f_max be set to 50MHz as well, no matter if max-frequency is set higher than 50MHz. We can simple solve this problem by assigning core clk as 200MHz in the first place and then let max-frequency property takes over it. Signed-off-by: Shawn Lin Change-Id: Idb2fdb8f68881d0286d977dc3718b74c30d3bc67 --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 9d76ec4ada65..beaa9c82e286 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -2462,8 +2462,9 @@ compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; reg = <0x0 0xfe310000 0x0 0x10000>; interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;