From c231916b68f3c5b90ff15b7bcebcb5cbf2fa3fa8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 19 Apr 2022 15:28:37 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Init PPLL to 1.1G PPLL 1.1G with pcie2 comboPHY TS3 can get better signal. Signed-off-by: Kever Yang Change-Id: I6af09906be88e7568b474b806161c3e1d6cd936e --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index b1d49e43c95d..8f1447caa6c8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2118,7 +2118,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>,