diff --git a/drivers/media/video/rk_camsys/camsys_internal.h b/drivers/media/video/rk_camsys/camsys_internal.h index c7b4e03e1a79..c5030d0653ea 100644 --- a/drivers/media/video/rk_camsys/camsys_internal.h +++ b/drivers/media/video/rk_camsys/camsys_internal.h @@ -207,9 +207,14 @@ reset on too high isp_clk rate will result in bus dead. The signoff isp_clk rate is 350M, and the recommended rate on reset from IC is NOT greater than 300M. +*v0.0x29.0: + 1) fix camera mipi phy config for rk3288. + CSIHOST_PHY_SHUTDOWNZ and CSIHOST_DPHY_RSTZ is + csi host control interface;so DPHY_RX1_SRC_SEL_MASK + should be set DPHY_RX1_SRC_SEL_CSI. */ -#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x28, 1) +#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x29, 0) #define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys" #define CAMSYS_PLATFORM_MARVIN_NAME "Platform_MarvinDev" diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3288.c b/drivers/media/video/rk_camsys/camsys_soc_rk3288.c index f7db3bcfc7b1..9c8769f464c1 100644 --- a/drivers/media/video/rk_camsys/camsys_soc_rk3288.c +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3288.c @@ -3,7 +3,6 @@ #include "camsys_soc_priv.h" #include "camsys_soc_rk3288.h" - struct mipiphy_hsfreqrange_s { unsigned int range_l; unsigned int range_h; @@ -43,51 +42,52 @@ static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = { }; - static int camsys_rk3288_mipiphy0_wr_reg( unsigned char addr, unsigned char data, camsys_mipiphy_soc_para_t *para) { - /*TESTCLK=1*/ + /* TESTCLK=1 */ write_grf_reg(GRF_SOC_CON14_OFFSET, - DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK); - /*TESTEN =1,TESTDIN=addr*/ + DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK); + /* TESTEN =1,TESTDIN=addr */ write_grf_reg(GRF_SOC_CON14_OFFSET, ((addr << DPHY_RX0_TESTDIN_OFFSET) - |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| + | DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN | DPHY_RX0_TESTEN_MASK)); - /*TESTCLK=0*/ + /* TESTCLK=0 */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK); - if (data != 0xff) { /*write data ?*/ - /*TESTEN =0,TESTDIN=data*/ + if (data != 0xff) { /* write data ? */ + /* TESTEN =0,TESTDIN=data */ write_grf_reg(GRF_SOC_CON14_OFFSET, ((data << DPHY_RX0_TESTDIN_OFFSET) | DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK)); - /*TESTCLK=1*/ + /* TESTCLK=1 */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK); } return 0; } + #if 0 static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr) { return read_grf_reg(GRF_SOC_STATUS21); } #endif + static int camsys_rk3288_mipiphy1_wr_reg( unsigned int phy_virt, unsigned char addr, unsigned char data) { - /*TESTEN =1,TESTDIN=addr*/ - write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000|addr)); - /*TESTCLK=0*/ + /* TESTEN =1,TESTDIN=addr */ + write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr)); + /* TESTCLK=0 */ write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000); - /*TESTEN =0,TESTDIN=data*/ - write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000|data)); - /*TESTCLK=1*/ + /* TESTEN =0,TESTDIN=data */ + write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data)); + /* TESTCLK=1 */ write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002); return 0; @@ -97,7 +97,7 @@ static int camsys_rk3288_mipiphy1_rd_reg( unsigned int phy_virt, unsigned char addr) { return (read_csihost_reg - (((CSIHOST_PHY_TEST_CTRL1)&0xff00)) >> 8); + (((CSIHOST_PHY_TEST_CTRL1) & 0xff00)) >> 8); } static int camsys_rk3288_mipihpy_cfg( @@ -107,6 +107,7 @@ camsys_mipiphy_soc_para_t *para) struct mipiphy_hsfreqrange_s *hsfreqrange_p; unsigned int phy_virt, phy_index; unsigned int *base; + unsigned int data_en_bit, data_en_num = 0; phy_index = para->phy->phy_index; if (para->camsys_dev->mipiphy[phy_index].reg != NULL) { @@ -122,14 +123,14 @@ camsys_mipiphy_soc_para_t *para) base = (unsigned int *) para->camsys_dev->devmems.registermem->vir_base; - *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4) - &= ~(0x0f<<8); + *(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL) / 4) + &= ~(0x0f << 8); camsys_trace(1, "mipi phy 0 standby!"); } else if (para->phy->phy_index == 1) { - /*SHUTDOWNZ=0*/ + /* SHUTDOWNZ=0 */ write_csihost_reg (CSIHOST_PHY_SHUTDOWNZ, 0x00000000); - /*RSTZ=0*/ + /* RSTZ=0 */ write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000); camsys_trace(1, "mipi phy 1 standby!"); @@ -141,10 +142,9 @@ camsys_mipiphy_soc_para_t *para) hsfreqrange_p = mipiphy_hsfreqrange; for (i = 0; i < - (sizeof(mipiphy_hsfreqrange)/ + (sizeof(mipiphy_hsfreqrange) / sizeof(struct mipiphy_hsfreqrange_s)); i++) { - if ((para->phy->bit_rate > hsfreqrange_p->range_l) && (para->phy->bit_rate <= hsfreqrange_p->range_h)) { hsfreqrange = hsfreqrange_p->cfg_bit; @@ -166,41 +166,41 @@ camsys_mipiphy_soc_para_t *para) | (para->phy->phy_index << MIPI_PHY_DPHYSEL_OFFSET_BIT)); - /* set lane num*/ + /* set lane num */ write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_ENABLE_MASK | (para->phy->data_en_bit << DPHY_RX0_ENABLE_OFFSET_BITS)); - /* set lan turndisab as 1*/ + /* set lan turndisab as 1 */ write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_TURN_DISABLE_MASK | (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS)); write_grf_reg(GRF_SOC_CON10_OFFSET, - (0x0<<4)|(0xf<<20)); + (0x0 << 4) | (0xf << 20)); /* set lan turnrequest as 0 */ write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_RX0_TURN_REQUEST_MASK | (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS)); - /*phy start*/ + /* phy start */ { - /*TESTCLK=1 */ + /* TESTCLK=1 */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK); - /*TESTCLR=1*/ + /* TESTCLR=1 */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK | DPHY_RX0_TESTCLR); udelay(100); - /*TESTCLR=0 zyc*/ + /* TESTCLR=0 zyc */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK); udelay(100); - /*set clock lane*/ + /* set clock lane */ camsys_rk3288_mipiphy0_wr_reg (0x34, 0x15, para); if (para->phy->data_en_bit >= 0x00) @@ -216,13 +216,13 @@ camsys_mipiphy_soc_para_t *para) (0x94, hsfreqrange, para); } - /*Normal operation*/ + /* Normal operation */ camsys_rk3288_mipiphy0_wr_reg(0x0, -1, para); - /*TESTCLK=1*/ + /* TESTCLK=1 */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK); - /*TESTEN =0 */ + /* TESTEN =0 */ write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN_MASK)); } @@ -230,97 +230,95 @@ camsys_mipiphy_soc_para_t *para) base = (unsigned int *) para->camsys_dev->devmems.registermem->vir_base; - *(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)/4) - |= (0x0f<<8); + *(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL) / 4) + |= (0x0f << 8); } else if (para->phy->phy_index == 1) { - + /* 7. Set BASEDIR_N to the desired values. */ + /* Real IC route must set firstly */ + write_grf_reg(GRF_SOC_CON14_OFFSET, + DPHY_TX1RX1_BASEDIR_REC + | DPHY_TX1RX1_BASEDIR_OFFSET); + /* 1'b1: MIPI PHY TX1RX1 1'b0: MIPI PHY RX0 */ write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (para->phy->phy_index << MIPI_PHY_DPHYSEL_OFFSET_BIT)); + /* 1'b1: CSI host 1'b0: DSI host1 */ write_grf_reg(GRF_SOC_CON6_OFFSET, DSI_CSI_TESTBUS_SEL_MASK | (1 << DSI_CSI_TESTBUS_SEL_OFFSET_BIT)); - + /* 1'b1: isp 1'b0: csi host */ write_grf_reg(GRF_SOC_CON14_OFFSET, - DPHY_RX1_SRC_SEL_ISP + DPHY_RX1_SRC_SEL_CSI | DPHY_RX1_SRC_SEL_MASK); + /* 1.Set RSTZ = 1'b0 */ + write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000); + /* 2. Set SHUTDOWNZ = 1'b0. */ + write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000); + /* 3. Set TESTCLEAR = 1'b1. */ + write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000001); + /* 4.Apply REFCLK signal with the appropriate frequency; */ + /* 5. Apply CFG_CLK signal with the appropriate frequency; */ + /* 6. Set MASTERSLAVEZ = 1'b1 (for MASTER) / 1'b0 (for SLAVE). */ write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK); - write_grf_reg(GRF_SOC_CON14_OFFSET, - DPHY_TX1RX1_BASEDIR_REC - | DPHY_TX1RX1_BASEDIR_OFFSET); - - /* set lane num*/ - write_grf_reg(GRF_SOC_CON9_OFFSET, - DPHY_TX1RX1_ENABLE_MASK - | (para->phy->data_en_bit - << DPHY_TX1RX1_ENABLE_OFFSET_BITS)); - /* set lan turndisab as 1*/ - write_grf_reg(GRF_SOC_CON9_OFFSET, - DPHY_TX1RX1_TURN_DISABLE_MASK - | (0xf - << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS)); - /* set lan turnrequest as 0 */ + /* 8. Set all REQUEST inputs to zero. */ write_grf_reg(GRF_SOC_CON15_OFFSET, - DPHY_TX1RX1_TURN_REQUEST_MASK - | (0x0 - << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS)); - - /*phy1 start*/ - { - /*SHUTDOWNZ=0*/ - write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000); - /*RSTZ=0*/ - write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000); - /*TESTCLK=1*/ - write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002); - /*TESTCLR=1 TESTCLK=1*/ - write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003); - udelay(100); - /*TESTCLR=0 TESTCLK=1*/ - write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002); - udelay(100); - - /*set clock lane*/ - camsys_rk3288_mipiphy1_wr_reg - (phy_virt, 0x34, 0x15); - if (para->phy->data_en_bit >= 0x00) - camsys_rk3288_mipiphy1_wr_reg - (phy_virt, 0x44, hsfreqrange); - if (para->phy->data_en_bit >= 0x01) - camsys_rk3288_mipiphy1_wr_reg - (phy_virt, 0x54, hsfreqrange); - if (para->phy->data_en_bit >= 0x04) { - camsys_rk3288_mipiphy1_wr_reg - (phy_virt, 0x84, hsfreqrange); - camsys_rk3288_mipiphy1_wr_reg - (phy_virt, 0x94, hsfreqrange); - } - - camsys_rk3288_mipiphy1_rd_reg - (phy_virt, 0x0); - /*TESTCLK=1*/ - write_csihost_reg - (CSIHOST_PHY_TEST_CTRL0, 0x00000002); - /*TESTEN =0*/ - write_csihost_reg - (CSIHOST_PHY_TEST_CTRL1, 0x00000000); - /*SHUTDOWNZ=1*/ - write_csihost_reg - (CSIHOST_PHY_SHUTDOWNZ, 0x00000001); - /*RSTZ=1*/ - write_csihost_reg - (CSIHOST_DPHY_RSTZ, 0x00000001); + DPHY_TX1RX1_TURN_REQUEST_MASK + | (0x0 + << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS)); + /* MIPI DPHY TX1RX1 disable turn around control */ + write_grf_reg(GRF_SOC_CON9_OFFSET, + DPHY_TX1RX1_TURN_DISABLE_MASK + | (0xf + << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS)); + /* MIPI DPHY TX1RX1 force lane into receive mode */ + /* wait for stop sta */ + write_grf_reg(GRF_SOC_CON9_OFFSET, + (DPHY_TX1RX1_FORCE_RX_MODE_OFFSET_BITS + << 4) + | DPHY_TX1RX1_FORCE_RX_MODE_MASK); + /* 9. Wait for 15 ns. */ + udelay(1); + /* 10. Set TESTCLR to low. */ + write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002); + /* 11. Wait for 15 ns. */ + udelay(1); + camsys_rk3288_mipiphy1_wr_reg(phy_virt, 0x34, 0x15); + /* 12. Configure Test Code 0x44 hsfreqrange. */ + camsys_rk3288_mipiphy1_wr_reg(phy_virt, 0x44, hsfreqrange); + camsys_rk3288_mipiphy1_rd_reg(phy_virt, 0x0); + write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002); + write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, 0x00000000); + /* 15.Set ENABLE_N=1'b1. */ + data_en_bit = para->phy->data_en_bit; + data_en_bit = data_en_bit >> 1; + data_en_num = 0; + while (data_en_bit) { + data_en_num++; + data_en_bit = data_en_bit >> 1; } + write_csihost_reg(CSIHOST_N_LANES, data_en_num); + write_grf_reg(GRF_SOC_CON14_OFFSET, + DPHY_TX1RX1_ENABLECLK + | DPHY_TX1RX1_ENABLECLK_MASK); + /* 16. Wait for 5 ns. */ + udelay(1); + /* 17. Set SHUTDOWNZ = 1'b1. */ + write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000001); + /* 18. Wait for 5 ns. */ + udelay(1); + /* 19.Set RSTZ = 1'b1 */ + write_csihost_reg + (CSIHOST_DPHY_RSTZ, 0x00000001); } else { camsys_err("mipi phy index %d is invalidate!", para->phy->phy_index); goto fail; - } +} camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)", para->phy->phy_index, @@ -352,12 +350,12 @@ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para) case Cif_IoDomain_Cfg: { para_int = (unsigned int *)cfg_para; if (*para_int < 28000000) { - /* 1.8v IO*/ + /* 1.8v IO */ __raw_writel (((1 << 1) | (1 << (1 + 16))), (void *)(camsys_dev->rk_grf_base + 0x0380)); } else { - /* 3.3v IO*/ + /* 3.3v IO */ __raw_writel (((0 << 1) | (1 << (1 + 16))), (void *)(camsys_dev->rk_grf_base + 0x0380)); @@ -385,14 +383,6 @@ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para) unsigned int reset; reset = (unsigned int)cfg_para; - /* - if (reset == 1) - cru_writel(0x40004000, 0x1d0); - else - cru_writel(0x40000000, 0x1d0); - camsys_trace(2, "Isp_SoftRst: %d", reset); - break; - */ if (reset == 1) __raw_writel(0x80, (void *)(camsys_dev->rk_isp_base + MRV_AFM_BASE + VI_IRCL)); @@ -411,4 +401,4 @@ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para) return 0; } -#endif /* CONFIG_ARM */ +#endif /* CONFIG_ARM */ diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3288.h b/drivers/media/video/rk_camsys/camsys_soc_rk3288.h index b34727f2a1ec..223cf98707b4 100644 --- a/drivers/media/video/rk_camsys/camsys_soc_rk3288.h +++ b/drivers/media/video/rk_camsys/camsys_soc_rk3288.h @@ -34,6 +34,7 @@ #define DPHY_TX1RX1_ENABLECLK (0x1 << 12) #define DPHY_TX1RX1_DISABLECLK (0x0 << 12) #define DPHY_RX1_SRC_SEL_ISP (0x1 << 13) +#define DPHY_RX1_SRC_SEL_CSI (0x0 << 13) #define DPHY_TX1RX1_SLAVEZ (0x0 << 14) #define DPHY_TX1RX1_BASEDIR_REC (0x1 << 15) @@ -73,6 +74,8 @@ #define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0) #define DPHY_TX1RX1_ENABLE_MASK (0xf << 28) #define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12) +#define DPHY_TX1RX1_FORCE_RX_MODE_MASK (0xf << 20) +#define DPHY_TX1RX1_FORCE_RX_MODE_OFFSET_BITS (0x0) /* *GRF_SOC_CON15