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ASoC: rockchip: rk817-codec: Reset DTOP_DIGEN_CLKE after finish digital registers

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This patch try to reset DTOP_DIGEN_CLKE during hook power up
after finish configure digital registers, avoid to the incorrect
work status.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Iaa7eb3ebf41d0a55ddf8005bcaeccae2c60656eb
This commit is contained in:
Xing Zheng
2021-12-09 20:01:11 +08:00
parent 13a543e8cc
commit c23c16b816
1 changed files with 14 additions and 0 deletions
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14
sound/soc/codecs/rk817_codec.c
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@@ -355,6 +355,13 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type)
playback_power_up_list[i].reg,
playback_power_up_list[i].value);
}
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
usleep_range(2000, 2500);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__);
}
if (type & RK817_CODEC_CAPTURE) {
@@ -368,6 +375,13 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type)
capture_power_up_list[i].value);
}
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
usleep_range(2000, 2500);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN);
DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__);
if (rk817->mic_in_differential)
snd_soc_component_update_bits(component,
RK817_CODEC_AMIC_CFG0,