diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
index 6dd21ea79688..4a9feb268675 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -1155,13 +1155,23 @@ next:
 #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
 	/* FIXME : consider pixel clocks over 200MHz */
 	if (vic == HDMI_CUSTOMBUILT) {
-		pr_info("[n2][%s] vic == HDMI_CUSTOMBUILT\n", __func__);
 		custom_timing = get_custom_timing();
 		p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10);
-		/* control od dividers */
-		p_enc[j].od1 = 1;
-		p_enc[j].od2 = 1;
-		p_enc[j].od3 = 2;
+		pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n",
+				__func__, custom_timing->frac_freq);
+		/* check if hpll clk output is under (100*10)MHz */
+		if (p_enc[j].hpll_clk_out < 1000000) {
+			p_enc[j].hpll_clk_out *= 4;
+			/* control od dividers */
+			p_enc[j].od1 = 4;
+			p_enc[j].od2 = 1;
+			p_enc[j].od3 = 2;
+		} else {
+			/* control od dividers */
+			p_enc[j].od1 = 1;
+			p_enc[j].od2 = 1;
+			p_enc[j].od3 = 2;
+		}
 	}
 #endif