From c4642391b1fe80f12ce3cbe535e2debd0402ab55 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 27 Feb 2024 16:33:24 +0800 Subject: [PATCH] drm/rockchip: vop2: adjust hfp and hbp for YUV420 output For RK3576 YUV420 output, hden signal introduce one cycle delay, so we need to adjust hfp and hbp to compatible with this design. Signed-off-by: Sandy Huang Change-Id: I272f3e145bfe216b1d76f6313c43180040590deb --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index eedd5cf57fe9..1dc23b775746 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -7364,6 +7364,15 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, } } + /* + * For RK3576 YUV420 output, hden signal introduce one cycle delay, + * so we need to adjust hfp and hbp to compatible with this design. + */ + if (vop2->version == VOP_VERSION_RK3576 && vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) { + adj_mode->hsync_start += 2; + adj_mode->hsync_end += 2; + } + drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)