From c491befc29917fe7d5e070c7a56e71f0466e3f2b Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Fri, 13 Mar 2020 15:49:28 +0800 Subject: [PATCH] dt-bindings: memory: update the define value about ds and odt for rv1126 Change-Id: Icbe34023412f3350cae978faae0444c557121274 Signed-off-by: YouMin Chen --- .../boot/dts/rv1126-dram-default-timing.dtsi | 78 ++-- include/dt-bindings/memory/rockchip-dram.h | 94 +++++ include/dt-bindings/memory/rv1126-dram.h | 360 +++++++----------- 3 files changed, 278 insertions(+), 254 deletions(-) create mode 100644 include/dt-bindings/memory/rockchip-dram.h diff --git a/arch/arm/boot/dts/rv1126-dram-default-timing.dtsi b/arch/arm/boot/dts/rv1126-dram-default-timing.dtsi index 019e7f4387cf..9e0b9627c6bb 100644 --- a/arch/arm/boot/dts/rv1126-dram-default-timing.dtsi +++ b/arch/arm/boot/dts/rv1126-dram-default-timing.dtsi @@ -12,8 +12,8 @@ ddr2_speed_bin = ; ddr3_speed_bin = ; ddr4_speed_bin = ; - pd_idle = <0>; - sr_idle = <0>; + pd_idle = <13>; + sr_idle = <93>; sr_mc_gate_idle = <0>; srpd_lite_idle = <0>; standby_idle = <0>; @@ -29,54 +29,54 @@ phy_ddr2_odt_dis_freq = <100>; ddr2_drv = ; ddr2_odt = ; - phy_ddr2_ca_drv = ; - phy_ddr2_ck_drv = ; - phy_ddr2_dq_drv = ; - phy_ddr2_odt = ; + phy_ddr2_ca_drv = ; + phy_ddr2_ck_drv = ; + phy_ddr2_dq_drv = ; + phy_ddr2_odt = ; - ddr3_odt_dis_freq = <400>; - phy_ddr3_odt_dis_freq = <400>; - ddr3_drv = ; + ddr3_odt_dis_freq = <333>; + phy_ddr3_odt_dis_freq = <333>; + ddr3_drv = ; ddr3_odt = ; - phy_ddr3_ca_drv = ; - phy_ddr3_ck_drv = ; - phy_ddr3_dq_drv = ; - phy_ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; - phy_lpddr2_odt_dis_freq = <666>; + phy_lpddr2_odt_dis_freq = <333>; lpddr2_drv = ; phy_lpddr2_ca_drv = ; - phy_lpddr2_ck_drv = ; + phy_lpddr2_ck_drv = ; phy_lpddr2_dq_drv = ; phy_lpddr2_odt = ; - lpddr3_odt_dis_freq = <400>; - phy_lpddr3_odt_dis_freq = <400>; - lpddr3_drv = ; - lpddr3_odt = ; - phy_lpddr3_ca_drv = ; - phy_lpddr3_ck_drv = ; - phy_lpddr3_dq_drv = ; - phy_lpddr3_odt = ; + lpddr3_odt_dis_freq = <333>; + phy_lpddr3_odt_dis_freq = <333>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; - lpddr4_odt_dis_freq = <800>; - phy_lpddr4_odt_dis_freq = <800>; - lpddr4_drv = ; - lpddr4_dq_odt = ; - lpddr4_ca_odt = ; - phy_lpddr4_ca_drv = ; - phy_lpddr4_ck_cs_drv = ; - phy_lpddr4_dq_drv = ; - phy_lpddr4_odt = ; + lpddr4_odt_dis_freq = <333>; + phy_lpddr4_odt_dis_freq = <333>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; - ddr4_odt_dis_freq = <666>; - phy_ddr4_odt_dis_freq = <666>; + ddr4_odt_dis_freq = <625>; + phy_ddr4_odt_dis_freq = <625>; ddr4_drv = ; - ddr4_odt = ; - phy_ddr4_ca_drv = ; - phy_ddr4_ck_drv = ; - phy_ddr4_dq_drv = ; - phy_ddr4_odt = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; /* * CA de-skew, one step is 20ps, range 0-63 diff --git a/include/dt-bindings/memory/rockchip-dram.h b/include/dt-bindings/memory/rockchip-dram.h new file mode 100644 index 000000000000..17e5e34b05c5 --- /dev/null +++ b/include/dt-bindings/memory/rockchip-dram.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_H + +#define DDR2_DS_FULL (0x0) +#define DDR2_DS_REDUCE (0x1 << 1) +#define DDR2_DS_MASK (0x1 << 1) + +#define DDR2_ODT_DIS (0x0) +#define DDR2_ODT_75ohm (0x1 << 2) +#define DDR2_ODT_150ohm (0x1 << 6) +#define DDR2_ODT_50ohm ((0x1 << 6) | (0x1 << 2)) /* optional */ +#define DDR2_ODT_MASK ((0x1 << 2) | (0x1 << 6)) + +#define DDR3_DS_40ohm (0x0) +#define DDR3_DS_34ohm (0x1 << 1) +#define DDR3_DS_MASK ((1 << 1) | (1 << 5)) + +#define DDR3_ODT_DIS (0x0) +#define DDR3_ODT_60ohm (0x1 << 2) +#define DDR3_ODT_120ohm (0x1 << 6) +#define DDR3_ODT_40ohm ((0x1 << 6) | (0x1 << 2)) +#define DDR3_ODT_MASK ((0x1 << 2) | (0x1 << 6) | (0x1 << 9)) + +#define DDR4_DS_34ohm (0x0) +#define DDR4_DS_48ohm (0x1 << 1) +#define DDR4_DS_MASK (0x3 << 1) + +#define DDR4_ODT_DIS (0x0) +#define DDR4_ODT_60ohm (0x1 << 8) +#define DDR4_ODT_120ohm (0x2 << 8) +#define DDR4_ODT_40ohm (0x3 << 8) +#define DDR4_ODT_240ohm (0x4 << 8) +#define DDR4_ODT_48ohm (0x5 << 8) +#define DDR4_ODT_80ohm (0x6 << 8) +#define DDR4_ODT_34ohm (0x7 << 8) +#define DDR4_ODT_MASK (0x7 << 8) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5) /* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7) /* optional */ +#define LP2_DS_MASK (0xf) + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) +#define LP3_DS_MASK (0xf) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (0x1) +#define LP3_ODT_120ohm (0x2) +#define LP3_ODT_240ohm (0x3) +#define LP3_ODT_MASK (0x3) + +#define LP4_PDDS_240ohm (0x1 << 3) +#define LP4_PDDS_120ohm (0x2 << 3) +#define LP4_PDDS_80ohm (0x3 << 3) +#define LP4_PDDS_60ohm (0x4 << 3) +#define LP4_PDDS_48ohm (0x5 << 3) +#define LP4_PDDS_40ohm (0x6 << 3) +#define LP4_PDDS_MASK (0x7 << 3) + +#define LP4_DQ_ODT_DIS (0x0) +#define LP4_DQ_ODT_240ohm (0x1) +#define LP4_DQ_ODT_120ohm (0x2) +#define LP4_DQ_ODT_80ohm (0x3) +#define LP4_DQ_ODT_60ohm (0x4) +#define LP4_DQ_ODT_48ohm (0x5) +#define LP4_DQ_ODT_40ohm (0x6) +#define LP4_DQ_ODT_MASK (0x7) + +#define LP4_CA_ODT_DIS (0x0) +#define LP4_CA_ODT_240ohm (0x1 << 4) +#define LP4_CA_ODT_120ohm (0x2 << 4) +#define LP4_CA_ODT_80ohm (0x3 << 4) +#define LP4_CA_ODT_60ohm (0x4 << 4) +#define LP4_CA_ODT_48ohm (0x5 << 4) +#define LP4_CA_ODT_40ohm (0x6 << 4) +#define LP4_CA_ODT_MASK (0x7 << 4) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_H */ diff --git a/include/dt-bindings/memory/rv1126-dram.h b/include/dt-bindings/memory/rv1126-dram.h index f33d873a5c6e..208227825044 100644 --- a/include/dt-bindings/memory/rv1126-dram.h +++ b/include/dt-bindings/memory/rv1126-dram.h @@ -6,226 +6,156 @@ #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H #define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H -#define DDR2_DS_FULL (0) -#define DDR2_DS_REDUCE (1) +#include -#define DDR2_ODT_DIS (0) -#define DDR2_ODT_50ohm (50) /* optional */ -#define DDR2_ODT_75ohm (75) -#define DDR2_ODT_150ohm (150) +#define PHY_DDR3_RON_DISABLE (0x0) +#define PHY_DDR3_RON_455ohm (0x1) +#define PHY_DDR3_RON_230ohm (0x2) +#define PHY_DDR3_RON_153ohm (0x3) +#define PHY_DDR3_RON_115ohm (0x4) +#define PHY_DDR3_RON_91ohm (0x5) +#define PHY_DDR3_RON_76ohm (0x6) +#define PHY_DDR3_RON_65ohm (0x7) +#define PHY_DDR3_RON_57ohm (0x10) +#define PHY_DDR3_RON_51ohm (0x11) +#define PHY_DDR3_RON_46ohm (0x12) +#define PHY_DDR3_RON_41ohm (0x13) +#define PHY_DDR3_RON_38ohm (0x14) +#define PHY_DDR3_RON_35ohm (0x15) +#define PHY_DDR3_RON_32ohm (0x16) +#define PHY_DDR3_RON_30ohm (0x17) +#define PHY_DDR3_RON_28ohm (0x18) +#define PHY_DDR3_RON_27ohm (0x19) +#define PHY_DDR3_RON_25ohm (0x1a) +#define PHY_DDR3_RON_24ohm (0x1b) +#define PHY_DDR3_RON_23ohm (0x1c) +#define PHY_DDR3_RON_22ohm (0x1d) +#define PHY_DDR3_RON_21ohm (0x1e) +#define PHY_DDR3_RON_20ohm (0x1f) -#define DDR3_DS_34ohm (34) -#define DDR3_DS_40ohm (40) +#define PHY_DDR3_RTT_DISABLE (0x0) +#define PHY_DDR3_RTT_561ohm (0x1) +#define PHY_DDR3_RTT_282ohm (0x2) +#define PHY_DDR3_RTT_188ohm (0x3) +#define PHY_DDR3_RTT_141ohm (0x4) +#define PHY_DDR3_RTT_113ohm (0x5) +#define PHY_DDR3_RTT_94ohm (0x6) +#define PHY_DDR3_RTT_81ohm (0x7) +#define PHY_DDR3_RTT_72ohm (0x10) +#define PHY_DDR3_RTT_64ohm (0x11) +#define PHY_DDR3_RTT_58ohm (0x12) +#define PHY_DDR3_RTT_52ohm (0x13) +#define PHY_DDR3_RTT_48ohm (0x14) +#define PHY_DDR3_RTT_44ohm (0x15) +#define PHY_DDR3_RTT_41ohm (0x16) +#define PHY_DDR3_RTT_38ohm (0x17) +#define PHY_DDR3_RTT_37ohm (0x18) +#define PHY_DDR3_RTT_34ohm (0x19) +#define PHY_DDR3_RTT_32ohm (0x1a) +#define PHY_DDR3_RTT_31ohm (0x1b) +#define PHY_DDR3_RTT_29ohm (0x1c) +#define PHY_DDR3_RTT_28ohm (0x1d) +#define PHY_DDR3_RTT_27ohm (0x1e) +#define PHY_DDR3_RTT_25ohm (0x1f) -#define DDR3_ODT_DIS (0) -#define DDR3_ODT_40ohm (40) -#define DDR3_ODT_60ohm (60) -#define DDR3_ODT_120ohm (120) +#define PHY_DDR4_LPDDR3_RON_DISABLE (0x0) +#define PHY_DDR4_LPDDR3_RON_482ohm (0x1) +#define PHY_DDR4_LPDDR3_RON_244ohm (0x2) +#define PHY_DDR4_LPDDR3_RON_162ohm (0x3) +#define PHY_DDR4_LPDDR3_RON_122ohm (0x4) +#define PHY_DDR4_LPDDR3_RON_97ohm (0x5) +#define PHY_DDR4_LPDDR3_RON_81ohm (0x6) +#define PHY_DDR4_LPDDR3_RON_69ohm (0x7) +#define PHY_DDR4_LPDDR3_RON_61ohm (0x10) +#define PHY_DDR4_LPDDR3_RON_54ohm (0x11) +#define PHY_DDR4_LPDDR3_RON_48ohm (0x12) +#define PHY_DDR4_LPDDR3_RON_44ohm (0x13) +#define PHY_DDR4_LPDDR3_RON_40ohm (0x14) +#define PHY_DDR4_LPDDR3_RON_37ohm (0x15) +#define PHY_DDR4_LPDDR3_RON_34ohm (0x16) +#define PHY_DDR4_LPDDR3_RON_32ohm (0x17) +#define PHY_DDR4_LPDDR3_RON_30ohm (0x18) +#define PHY_DDR4_LPDDR3_RON_28ohm (0x19) +#define PHY_DDR4_LPDDR3_RON_27ohm (0x1a) +#define PHY_DDR4_LPDDR3_RON_25ohm (0x1b) +#define PHY_DDR4_LPDDR3_RON_24ohm (0x1c) +#define PHY_DDR4_LPDDR3_RON_23ohm (0x1d) +#define PHY_DDR4_LPDDR3_RON_22ohm (0x1e) +#define PHY_DDR4_LPDDR3_RON_21ohm (0x1f) -#define LP2_DS_34ohm (34) -#define LP2_DS_40ohm (40) -#define LP2_DS_48ohm (48) -#define LP2_DS_60ohm (60) -#define LP2_DS_68_6ohm (68) /* optional */ -#define LP2_DS_80ohm (80) -#define LP2_DS_120ohm (120) /* optional */ +#define PHY_DDR4_LPDDR3_RTT_DISABLE (0x0) +#define PHY_DDR4_LPDDR3_RTT_586ohm (0x1) +#define PHY_DDR4_LPDDR3_RTT_294ohm (0x2) +#define PHY_DDR4_LPDDR3_RTT_196ohm (0x3) +#define PHY_DDR4_LPDDR3_RTT_148ohm (0x4) +#define PHY_DDR4_LPDDR3_RTT_118ohm (0x5) +#define PHY_DDR4_LPDDR3_RTT_99ohm (0x6) +#define PHY_DDR4_LPDDR3_RTT_85ohm (0x7) +#define PHY_DDR4_LPDDR3_RTT_76ohm (0x10) +#define PHY_DDR4_LPDDR3_RTT_67ohm (0x11) +#define PHY_DDR4_LPDDR3_RTT_60ohm (0x12) +#define PHY_DDR4_LPDDR3_RTT_55ohm (0x13) +#define PHY_DDR4_LPDDR3_RTT_50ohm (0x14) +#define PHY_DDR4_LPDDR3_RTT_46ohm (0x15) +#define PHY_DDR4_LPDDR3_RTT_43ohm (0x16) +#define PHY_DDR4_LPDDR3_RTT_40ohm (0x17) +#define PHY_DDR4_LPDDR3_RTT_38ohm (0x18) +#define PHY_DDR4_LPDDR3_RTT_36ohm (0x19) +#define PHY_DDR4_LPDDR3_RTT_34ohm (0x1a) +#define PHY_DDR4_LPDDR3_RTT_32ohm (0x1b) +#define PHY_DDR4_LPDDR3_RTT_31ohm (0x1c) +#define PHY_DDR4_LPDDR3_RTT_29ohm (0x1d) +#define PHY_DDR4_LPDDR3_RTT_28ohm (0x1e) +#define PHY_DDR4_LPDDR3_RTT_27ohm (0x1f) -#define LP3_DS_34ohm (34) -#define LP3_DS_40ohm (40) -#define LP3_DS_48ohm (48) -#define LP3_DS_60ohm (60) -#define LP3_DS_80ohm (80) -#define LP3_DS_34D_40U (3440) -#define LP3_DS_40D_48U (4048) -#define LP3_DS_34D_48U (3448) +#define PHY_LPDDR4_RON_DISABLE (0x0) +#define PHY_LPDDR4_RON_501ohm (0x1) +#define PHY_LPDDR4_RON_253ohm (0x2) +#define PHY_LPDDR4_RON_168ohm (0x3) +#define PHY_LPDDR4_RON_126ohm (0x4) +#define PHY_LPDDR4_RON_101ohm (0x5) +#define PHY_LPDDR4_RON_84ohm (0x6) +#define PHY_LPDDR4_RON_72ohm (0x7) +#define PHY_LPDDR4_RON_63ohm (0x10) +#define PHY_LPDDR4_RON_56ohm (0x11) +#define PHY_LPDDR4_RON_50ohm (0x12) +#define PHY_LPDDR4_RON_46ohm (0x13) +#define PHY_LPDDR4_RON_42ohm (0x14) +#define PHY_LPDDR4_RON_38ohm (0x15) +#define PHY_LPDDR4_RON_36ohm (0x16) +#define PHY_LPDDR4_RON_33ohm (0x17) +#define PHY_LPDDR4_RON_31ohm (0x18) +#define PHY_LPDDR4_RON_29ohm (0x19) +#define PHY_LPDDR4_RON_28ohm (0x1a) +#define PHY_LPDDR4_RON_26ohm (0x1b) +#define PHY_LPDDR4_RON_25ohm (0x1c) +#define PHY_LPDDR4_RON_24ohm (0x1d) +#define PHY_LPDDR4_RON_23ohm (0x1e) +#define PHY_LPDDR4_RON_22ohm (0x1f) -#define LP3_ODT_DIS (0) -#define LP3_ODT_60ohm (60) -#define LP3_ODT_120ohm (120) -#define LP3_ODT_240ohm (240) - -#define LP4_PDDS_40ohm (40) -#define LP4_PDDS_48ohm (48) -#define LP4_PDDS_60ohm (60) -#define LP4_PDDS_80ohm (80) -#define LP4_PDDS_120ohm (120) -#define LP4_PDDS_240ohm (240) - -#define LP4_DQ_ODT_40ohm (40) -#define LP4_DQ_ODT_48ohm (48) -#define LP4_DQ_ODT_60ohm (60) -#define LP4_DQ_ODT_80ohm (80) -#define LP4_DQ_ODT_120ohm (120) -#define LP4_DQ_ODT_240ohm (240) -#define LP4_DQ_ODT_DIS (0) - -#define LP4_CA_ODT_40ohm (40) -#define LP4_CA_ODT_48ohm (48) -#define LP4_CA_ODT_60ohm (60) -#define LP4_CA_ODT_80ohm (80) -#define LP4_CA_ODT_120ohm (120) -#define LP4_CA_ODT_240ohm (240) -#define LP4_CA_ODT_DIS (0) - -#define DDR4_DS_34ohm (34) -#define DDR4_DS_48ohm (48) -#define DDR4_RTT_NOM_DIS (0) -#define DDR4_RTT_NOM_60ohm (60) -#define DDR4_RTT_NOM_120ohm (120) -#define DDR4_RTT_NOM_40ohm (40) -#define DDR4_RTT_NOM_240ohm (240) -#define DDR4_RTT_NOM_48ohm (48) -#define DDR4_RTT_NOM_80ohm (80) -#define DDR4_RTT_NOM_34ohm (34) - -#define PHY_DDR3_RON_DISABLE (0) -#define PHY_DDR3_RON_506ohm (1) -#define PHY_DDR3_RON_253ohm (2) -#define PHY_DDR3_RON_169hm (3) -#define PHY_DDR3_RON_127ohm (4) -#define PHY_DDR3_RON_101ohm (5) -#define PHY_DDR3_RON_84ohm (6) -#define PHY_DDR3_RON_72ohm (7) -#define PHY_DDR3_RON_63ohm (16) -#define PHY_DDR3_RON_56ohm (17) -#define PHY_DDR3_RON_51ohm (18) -#define PHY_DDR3_RON_46ohm (19) -#define PHY_DDR3_RON_42ohm (20) -#define PHY_DDR3_RON_39ohm (21) -#define PHY_DDR3_RON_36ohm (22) -#define PHY_DDR3_RON_34ohm (23) -#define PHY_DDR3_RON_32ohm (24) -#define PHY_DDR3_RON_30ohm (25) -#define PHY_DDR3_RON_28ohm (26) -#define PHY_DDR3_RON_27ohm (27) -#define PHY_DDR3_RON_25ohm (28) -#define PHY_DDR3_RON_24ohm (29) -#define PHY_DDR3_RON_23ohm (30) -#define PHY_DDR3_RON_22ohm (31) - -#define PHY_DDR3_RTT_DISABLE (0) -#define PHY_DDR3_RTT_953ohm (1) -#define PHY_DDR3_RTT_483ohm (2) -#define PHY_DDR3_RTT_320ohm (3) -#define PHY_DDR3_RTT_241ohm (4) -#define PHY_DDR3_RTT_193ohm (5) -#define PHY_DDR3_RTT_161ohm (6) -#define PHY_DDR3_RTT_138ohm (7) -#define PHY_DDR3_RTT_121ohm (16) -#define PHY_DDR3_RTT_107ohm (17) -#define PHY_DDR3_RTT_97ohm (18) -#define PHY_DDR3_RTT_88ohm (19) -#define PHY_DDR3_RTT_80ohm (20) -#define PHY_DDR3_RTT_74ohm (21) -#define PHY_DDR3_RTT_69ohm (22) -#define PHY_DDR3_RTT_64ohm (23) -#define PHY_DDR3_RTT_60ohm (24) -#define PHY_DDR3_RTT_57ohm (25) -#define PHY_DDR3_RTT_54ohm (26) -#define PHY_DDR3_RTT_51ohm (27) -#define PHY_DDR3_RTT_48ohm (28) -#define PHY_DDR3_RTT_46ohm (29) -#define PHY_DDR3_RTT_44ohm (30) -#define PHY_DDR3_RTT_42ohm (31) - -#define PHY_DDR4_LPDDR3_RON_DISABLE (0) -#define PHY_DDR4_LPDDR3_RON_570ohm (1) -#define PHY_DDR4_LPDDR3_RON_285ohm (2) -#define PHY_DDR4_LPDDR3_RON_190ohm (3) -#define PHY_DDR4_LPDDR3_RON_142ohm (4) -#define PHY_DDR4_LPDDR3_RON_114ohm (5) -#define PHY_DDR4_LPDDR3_RON_95ohm (6) -#define PHY_DDR4_LPDDR3_RON_81ohm (7) -#define PHY_DDR4_LPDDR3_RON_71ohm (16) -#define PHY_DDR4_LPDDR3_RON_63ohm (17) -#define PHY_DDR4_LPDDR3_RON_57ohm (18) -#define PHY_DDR4_LPDDR3_RON_52ohm (19) -#define PHY_DDR4_LPDDR3_RON_47ohm (20) -#define PHY_DDR4_LPDDR3_RON_44ohm (21) -#define PHY_DDR4_LPDDR3_RON_41ohm (22) -#define PHY_DDR4_LPDDR3_RON_38ohm (23) -#define PHY_DDR4_LPDDR3_RON_36ohm (24) -#define PHY_DDR4_LPDDR3_RON_34ohm (25) -#define PHY_DDR4_LPDDR3_RON_32ohm (26) -#define PHY_DDR4_LPDDR3_RON_30ohm (27) -#define PHY_DDR4_LPDDR3_RON_28ohm (28) -#define PHY_DDR4_LPDDR3_RON_27ohm (29) -#define PHY_DDR4_LPDDR3_RON_26ohm (30) -#define PHY_DDR4_LPDDR3_RON_25ohm (31) - -#define PHY_DDR4_LPDDR3_RTT_DISABLE (0) -#define PHY_DDR4_LPDDR3_RTT_973ohm (1) -#define PHY_DDR4_LPDDR3_RTT_493ohm (2) -#define PHY_DDR4_LPDDR3_RTT_327ohm (3) -#define PHY_DDR4_LPDDR3_RTT_247ohm (4) -#define PHY_DDR4_LPDDR3_RTT_197ohm (5) -#define PHY_DDR4_LPDDR3_RTT_164ohm (6) -#define PHY_DDR4_LPDDR3_RTT_141ohm (7) -#define PHY_DDR4_LPDDR3_RTT_123ohm (16) -#define PHY_DDR4_LPDDR3_RTT_109ohm (17) -#define PHY_DDR4_LPDDR3_RTT_99ohm (18) -#define PHY_DDR4_LPDDR3_RTT_90ohm (19) -#define PHY_DDR4_LPDDR3_RTT_82ohm (20) -#define PHY_DDR4_LPDDR3_RTT_76ohm (21) -#define PHY_DDR4_LPDDR3_RTT_70ohm (22) -#define PHY_DDR4_LPDDR3_RTT_66ohm (23) -#define PHY_DDR4_LPDDR3_RTT_62ohm (24) -#define PHY_DDR4_LPDDR3_RTT_58ohm (25) -#define PHY_DDR4_LPDDR3_RTT_55ohm (26) -#define PHY_DDR4_LPDDR3_RTT_52ohm (27) -#define PHY_DDR4_LPDDR3_RTT_49ohm (28) -#define PHY_DDR4_LPDDR3_RTT_47ohm (29) -#define PHY_DDR4_LPDDR3_RTT_45ohm (30) -#define PHY_DDR4_LPDDR3_RTT_43ohm (31) - -#define PHY_LPDDR4_RON_DISABLE (0) -#define PHY_LPDDR4_RON_606ohm (1) -#define PHY_LPDDR4_RON_303ohm (2) -#define PHY_LPDDR4_RON_202ohm (3) -#define PHY_LPDDR4_RON_152ohm (4) -#define PHY_LPDDR4_RON_121ohm (5) -#define PHY_LPDDR4_RON_101ohm (6) -#define PHY_LPDDR4_RON_87ohm (7) -#define PHY_LPDDR4_RON_76ohm (16) -#define PHY_LPDDR4_RON_67ohm (17) -#define PHY_LPDDR4_RON_61ohm (18) -#define PHY_LPDDR4_RON_55ohm (19) -#define PHY_LPDDR4_RON_51ohm (20) -#define PHY_LPDDR4_RON_47ohm (21) -#define PHY_LPDDR4_RON_43ohm (22) -#define PHY_LPDDR4_RON_40ohm (23) -#define PHY_LPDDR4_RON_38ohm (24) -#define PHY_LPDDR4_RON_36ohm (25) -#define PHY_LPDDR4_RON_34ohm (26) -#define PHY_LPDDR4_RON_32ohm (27) -#define PHY_LPDDR4_RON_30ohm (28) -#define PHY_LPDDR4_RON_29ohm (29) -#define PHY_LPDDR4_RON_28ohm (30) -#define PHY_LPDDR4_RON_26ohm (31) - -#define PHY_LPDDR4_RTT_DISABLE (0) -#define PHY_LPDDR4_RTT_998ohm (1) -#define PHY_LPDDR4_RTT_506ohm (2) -#define PHY_LPDDR4_RTT_336ohm (3) -#define PHY_LPDDR4_RTT_253ohm (4) -#define PHY_LPDDR4_RTT_202ohm (5) -#define PHY_LPDDR4_RTT_169ohm (6) -#define PHY_LPDDR4_RTT_144ohm (7) -#define PHY_LPDDR4_RTT_127ohm (16) -#define PHY_LPDDR4_RTT_112ohm (17) -#define PHY_LPDDR4_RTT_101ohm (18) -#define PHY_LPDDR4_RTT_92ohm (19) -#define PHY_LPDDR4_RTT_84ohm (20) -#define PHY_LPDDR4_RTT_78ohm (21) -#define PHY_LPDDR4_RTT_72ohm (22) -#define PHY_LPDDR4_RTT_67ohm (23) -#define PHY_LPDDR4_RTT_63ohm (24) -#define PHY_LPDDR4_RTT_60ohm (25) -#define PHY_LPDDR4_RTT_56ohm (26) -#define PHY_LPDDR4_RTT_53ohm (27) -#define PHY_LPDDR4_RTT_51ohm (28) -#define PHY_LPDDR4_RTT_48ohm (29) -#define PHY_LPDDR4_RTT_46ohm (30) -#define PHY_LPDDR4_RTT_44ohm (31) +#define PHY_LPDDR4_RTT_DISABLE (0x0) +#define PHY_LPDDR4_RTT_604ohm (0x1) +#define PHY_LPDDR4_RTT_303ohm (0x2) +#define PHY_LPDDR4_RTT_202ohm (0x3) +#define PHY_LPDDR4_RTT_152ohm (0x4) +#define PHY_LPDDR4_RTT_122ohm (0x5) +#define PHY_LPDDR4_RTT_101ohm (0x6) +#define PHY_LPDDR4_RTT_87ohm (0x7) +#define PHY_LPDDR4_RTT_78ohm (0x10) +#define PHY_LPDDR4_RTT_69ohm (0x11) +#define PHY_LPDDR4_RTT_62ohm (0x12) +#define PHY_LPDDR4_RTT_56ohm (0x13) +#define PHY_LPDDR4_RTT_52ohm (0x14) +#define PHY_LPDDR4_RTT_48ohm (0x15) +#define PHY_LPDDR4_RTT_44ohm (0x16) +#define PHY_LPDDR4_RTT_41ohm (0x17) +#define PHY_LPDDR4_RTT_39ohm (0x18) +#define PHY_LPDDR4_RTT_37ohm (0x19) +#define PHY_LPDDR4_RTT_35ohm (0x1a) +#define PHY_LPDDR4_RTT_33ohm (0x1b) +#define PHY_LPDDR4_RTT_32ohm (0x1c) +#define PHY_LPDDR4_RTT_30ohm (0x1d) +#define PHY_LPDDR4_RTT_29ohm (0x1e) +#define PHY_LPDDR4_RTT_27ohm (0x1f) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/