From c4cf9286aa0a19ae91c30ebf9620e976183310da Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Thu, 12 Mar 2020 15:08:27 +0800 Subject: [PATCH] drm/rockchip: dsi: update GRF_REG_FIELD update this for support some GRF's register offset over 0x10000 Signed-off-by: Nickey Yang Change-Id: I8427e17fafa537980f2233483c23e8f3511fd9e9 --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index f72b3fa46948..1bd7eb7c2728 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -213,7 +213,7 @@ enum operation_mode { COMMAND_MODE, }; -#define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) +#define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) enum grf_reg_fields { DPIUPDATECFG, @@ -300,15 +300,15 @@ static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : dsi->pdata->dsi0_grf_reg_fields[index]; - u16 reg; + u32 reg; u8 msb, lsb; if (!field) return; - reg = (field >> 16) & 0xffff; - lsb = (field >> 8) & 0xff; - msb = (field >> 0) & 0xff; + reg = (field >> 10) & 0x3ffff; + lsb = (field >> 5) & 0x1f; + msb = (field >> 0) & 0x1f; regmap_write(dsi->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16)); }