From c56568e8bfae4236f50f02604801fa0a071c1cb0 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 7 Jun 2021 11:30:46 +0800 Subject: [PATCH] clk: rockchip: add flag CLK_GATE_NO_SET_RATE Add CLK_GATE_NO_SET_RATE for gate clks not allowed to support setting rate. Signed-off-by: Elaine Zhang Change-Id: Iddd1c958661f8ff9217b8781426314b0619367db --- drivers/clk/rockchip/clk.c | 3 ++- include/linux/clk-provider.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 08de23d0bc36..260c5bd6ffa3 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -618,7 +618,8 @@ void __init rockchip_clk_register_branches( flags, &ctx->lock); break; case branch_gate: - flags |= CLK_SET_RATE_PARENT; + if (!(list->gate_flags & CLK_GATE_NO_SET_RATE)) + flags |= CLK_SET_RATE_PARENT; clk = clk_register_gate(NULL, list->name, list->parent_names[0], flags, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b59dc97e1d3c..402e3639a029 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -445,6 +445,8 @@ void of_fixed_clk_setup(struct device_node *np); * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. + * CLK_GATE_NO_SET_RATE - The Gate not allowed to set rate. + * And not allowed to set parent rate. */ struct clk_gate { struct clk_hw hw; @@ -458,6 +460,7 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) +#define CLK_GATE_NO_SET_RATE BIT(3) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name,