From c677d85122bc52fc189e28c9fda00a126aacd4f0 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Mon, 17 Feb 2025 10:36:40 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588: Add qos_gic600_m0 and
 qos_gic600_m1

Change-Id: Icb547d8765d345e979a12c98f52ddecad547c388
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index aa5d7d528517..78ebdd048e74 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -3364,6 +3364,8 @@
 				clocks = <&cru PCLK_PHP_ROOT>,
 					 <&cru ACLK_PCIE_ROOT>,
 					 <&cru ACLK_PHP_ROOT>;
+				pm_qos = <&qos_gic600_m0>,
+					 <&qos_gic600_m1>;
 			};
 			power-domain@RK3588_PD_SDIO {
 				reg = <RK3588_PD_SDIO>;
@@ -5251,6 +5253,16 @@
 		reg = <0x0 0xfdf39000 0x0 0x20>;
 	};
 
+	qos_gic600_m0: qos@fdf3a000 {
+		compatible = "syscon";
+		reg = <0x0 0xfdf3a000 0x0 0x20>;
+	};
+
+	qos_gic600_m1: qos@fdf3a200 {
+		compatible = "syscon";
+		reg = <0x0 0xfdf3a200 0x0 0x20>;
+	};
+
 	qos_sdmmc: qos@fdf3d800 {
 		compatible = "syscon";
 		reg = <0x0 0xfdf3d800 0x0 0x20>;