From 1a24edd2ee4656610829fdda69e53fdc6fa4ee99 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:50 +0300 Subject: [PATCH 1/8] arm: dts: lpc32xx: change include syntax to be C preprocessor friendly The change replaces /include/ to #include in lpc32xx.dtsi and derivatives, it is required, if C preprocessor is intended to be used over dtsi/dts files, otherwise errors like one below are generated: Error: ea3250.dts:15.1-9 syntax error FATAL ERROR: Unable to parse input tree Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 2 +- arch/arm/boot/dts/lpc32xx.dtsi | 2 +- arch/arm/boot/dts/phy3250.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index a4ba31b23c88..121d0328a0d6 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "lpc32xx.dtsi" +#include "lpc32xx.dtsi" / { model = "Embedded Artists LPC3250 board based on NXP LPC3250"; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 3abebb75fc57..f35e9822ddec 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -11,7 +11,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nxp,lpc3220"; diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 90fdbd77f274..2a2d2cfd02c8 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "lpc32xx.dtsi" +#include "lpc32xx.dtsi" / { model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; From 25de7c961588f10df3d5c8d5b54d70fe39b7d256 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:51 +0300 Subject: [PATCH 2/8] arm: dts: lpc32xx: add labels to all defined peripheral nodes To simplify writing of dts files for all lpc32xx.dtsi users who adjust device node properties, add labels to all defined peripheral device nodes in lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index f35e9822ddec..00570b308b23 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -49,7 +49,7 @@ status = "disabled"; }; - dma@31000000 { + dma: dma@31000000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; interrupts = <0x1c 0>; @@ -58,21 +58,21 @@ /* * Enable either ohci or usbd (gadget)! */ - ohci@31020000 { + ohci: ohci@31020000 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x31020000 0x300>; interrupts = <0x3b 0>; status = "disabled"; }; - usbd@31020000 { + usbd: usbd@31020000 { compatible = "nxp,lpc3220-udc"; reg = <0x31020000 0x300>; interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; status = "disabled"; }; - clcd@31040000 { + clcd: clcd@31040000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <0x0e 0>; @@ -118,7 +118,7 @@ reg = <0x20094000 0x1000>; }; - sd@20098000 { + sd: sd@20098000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <0x0f 0>, <0x0d 0>; @@ -243,7 +243,7 @@ status = "disabled"; }; - rtc@40024000 { + rtc: rtc@40024000 { compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; interrupts = <0x34 0>; @@ -256,7 +256,7 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; - watchdog@4003C000 { + watchdog: watchdog@4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; }; @@ -268,21 +268,21 @@ * them */ - adc@40048000 { + adc: adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; status = "disabled"; }; - tsc@40048000 { + tsc: tsc@40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; status = "disabled"; }; - key@40050000 { + key: key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; interrupts = <54 0>; From 246d8fc33e570b7c1e69cdbf395fcfcee58785cc Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:52 +0300 Subject: [PATCH 3/8] arm: dts: lpc32xx: add reg property to cpu device node According to device tree bindings for ARM cpus cpu node must contain a reg property for enumeration scheme. The change adds reg = <0x0> indicating that the processor does not have CPU identification register and updates cell settings. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 00570b308b23..fb0e9ae8238f 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -18,12 +18,13 @@ interrupt-parent = <&mic>; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; }; From 2a6c6563313dd5c96277e4a3368df65e268bcc9b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:53 +0300 Subject: [PATCH 4/8] arm: dts: lpc32xx: add device node for the second pwm controller LPC32xx SoCs have two independent PWM controllers, they have different clock parents, clock gates and even slightly different controls, each of these two PWM controllers has one output channel. Due to almost similar controls arranged in a row it is incorrectly assumed that there is one PWM controller with two channels, fix this problem in lpc32xx.dtsi, which at the moment prevents separate configuration of different clock parents and gates for both PWM controllers. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index fb0e9ae8238f..be829926f860 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -290,9 +290,15 @@ status = "disabled"; }; - pwm: pwm@4005C000 { + pwm1: pwm@4005C000 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x8>; + reg = <0x4005C000 0x4>; + status = "disabled"; + }; + + pwm2: pwm@4005C004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005C004 0x4>; status = "disabled"; }; }; From cae59490674cf8dab153c6b1350247228b3fc972 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:54 +0300 Subject: [PATCH 5/8] arm: dts: ea3250/phy3250: specify phys memory offset for lpc32xx boards In case if SDRAM memory region is not populated by a bootloader, provide this value in device trees for EA3250 and PHY3250 boards. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 2 +- arch/arm/boot/dts/phy3250.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index 121d0328a0d6..392430b25154 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -22,7 +22,7 @@ memory { device_type = "memory"; - reg = <0 0x4000000>; + reg = <0x80000000 0x4000000>; }; ahb { diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 2a2d2cfd02c8..79a20f7730f3 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -22,7 +22,7 @@ memory { device_type = "memory"; - reg = <0 0x4000000>; + reg = <0x80000000 0x4000000>; }; ahb { From f83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:55 +0300 Subject: [PATCH 6/8] arm: dts: lpc32xx: add external memory controller device node The change adds a description of ARM PrimeCell PL175 memory controller, which is found on NXP LPC32xx SoCs. The controller supports up to 4 static memory devices mapped to 0xE000 0000 - 0xE3FF FFFF physical memory area. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index be829926f860..a595a4b772d4 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -32,7 +32,8 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; + ranges = <0x20000000 0x20000000 0x30000000>, + <0xe0000000 0xe0000000 0x04000000>; /* * Enable either SLC or MLC @@ -86,6 +87,19 @@ interrupts = <0x1d 0>; }; + emc: memory-controller@31080000 { + compatible = "arm,pl175", "arm,primecell"; + reg = <0x31080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe0000000 0x01000000>, + <1 0xe1000000 0x01000000>, + <2 0xe2000000 0x01000000>, + <3 0xe3000000 0x01000000>; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; From c1aa70072cfb95d28bd5b63848f9b37e57273f18 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:41:06 +0300 Subject: [PATCH 7/8] arm: dts: lpc32xx: add device nodes for standard timers NXP LPC32xx SoCs have 6 standard timers, add device nodes to describe them. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a595a4b772d4..ba91b203c8c1 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -271,11 +271,31 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; + timer4: timer@4002C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002C000 0x1000>; + interrupts = <0x3 0>; + status = "disabled"; + }; + + timer5: timer@40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <0x4 0>; + status = "disabled"; + }; + watchdog: watchdog@4003C000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; }; + timer0: timer@40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + interrupts = <0x10 0>; + }; + /* * TSC vs. ADC: Since those two share the same * hardware, you need to choose from one of the @@ -297,6 +317,12 @@ status = "disabled"; }; + timer1: timer@4004C000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004C000 0x1000>; + interrupts = <0x11 0>; + }; + key: key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; @@ -304,6 +330,13 @@ status = "disabled"; }; + timer2: timer@40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <0x12 0>; + status = "disabled"; + }; + pwm1: pwm@4005C000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; @@ -315,6 +348,13 @@ reg = <0x4005C004 0x4>; status = "disabled"; }; + + timer3: timer@40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <0x13 0>; + status = "disabled"; + }; }; }; }; From aa29efb445f11506daca0db934331f144b38ddc4 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 18 Oct 2015 00:35:57 +0300 Subject: [PATCH 8/8] arm: dts: lpc32xx: move USB controller subdevices into own device node NXP LPC32xx SoC has one USB OTG controller, which is supposed to work with an external phy (default is NXP ISP1301). Practically the USB controller contains 5 subdevices: - host controller 0x3102 0000 -- 0x3102 00FF - OTG controller 0x3102 0100 -- 0x3102 01FF - device controller 0x3102 0200 -- 0x3102 02FF - I2C controller 0x3102 0300 -- 0x3102 03FF - clock controller 0x3102 0F00 -- 0x3102 0FFF The USB controller can be considered as a "bus", because the subdevices above are relatively independent, for example I2C controller is the same as other two general purpose I2C controllers found on SoC. The change is not intended to modify any logic, but it rearranges existing device nodes, in future it is planned to add a USB clock controller device node into the same group. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 37 ++++++++++-------------- arch/arm/boot/dts/lpc32xx.dtsi | 53 +++++++++++++++++++--------------- arch/arm/boot/dts/phy3250.dts | 37 ++++++++++-------------- 3 files changed, 60 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index 392430b25154..a4a281fe82af 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -31,19 +31,6 @@ use-iram; }; - /* Here, choose exactly one from: ohci, usbd */ - ohci@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; - -/* - usbd@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; -*/ - /* 128MB Flash via SLC NAND controller */ slc: flash@20020000 { status = "okay"; @@ -130,15 +117,6 @@ clock-frequency = <100000>; }; - i2cusb: i2c@31020300 { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; - }; - sd@20098000 { wp-gpios = <&pca9532 5 0>; cd-gpios = <&pca9532 4 0>; @@ -279,3 +257,18 @@ }; }; }; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; +}; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index ba91b203c8c1..c85cf979725e 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -57,21 +57,37 @@ interrupts = <0x1c 0>; }; - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci@31020000 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x31020000 0x300>; - interrupts = <0x3b 0>; - status = "disabled"; - }; + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; - usbd: usbd@31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - status = "disabled"; + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: ohci@0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupts = <0x3b 0>; + status = "disabled"; + }; + + usbd: usbd@0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>; + interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; + status = "disabled"; + }; + + i2cusb: i2c@300 { + compatible = "nxp,pnx-i2c"; + reg = <0x300 0x100>; + interrupts = <0x3f 0>; + #address-cells = <1>; + #size-cells = <0>; + pnx,timeout = <0x64>; + }; }; clcd: clcd@31040000 { @@ -207,15 +223,6 @@ status = "disabled"; #pwm-cells = <2>; }; - - i2cusb: i2c@31020300 { - compatible = "nxp,pnx-i2c"; - reg = <0x31020300 0x100>; - interrupts = <0x3f 0>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - }; }; fab { diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 79a20f7730f3..7d253bb6265a 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -31,19 +31,6 @@ use-iram; }; - /* Here, choose exactly one from: ohci, usbd */ - ohci@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; - -/* - usbd@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; -*/ - clcd@31040000 { status = "okay"; }; @@ -123,15 +110,6 @@ clock-frequency = <100000>; }; - i2cusb: i2c@31020300 { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - }; - ssp0: ssp@20084000 { #address-cells = <1>; #size-cells = <0>; @@ -200,3 +178,18 @@ }; }; }; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2c { + compatible = "nxp,isp1301"; + reg = <0x2c>; + }; +};