From c7d3eae2d2af15cdc9b09340aeb3fd06d4230e43 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 6 Jun 2022 07:31:59 +0000 Subject: [PATCH] clk: rockchip: rk3588: Fix coding style Use its own RK3588_PLLCON(), maybe RK3399_PLLCON() was brought when copy RK3399 code. Fixes: 58c1fa2ef200 ("clk: rockchip: add pll type for RK3588") Signed-off-by: Joseph Chen Change-Id: I551c1d39073f2eba4837bd702f9c2172bfecbd65 --- drivers/clk/rockchip/clk-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 402548937f87..315cbb73e3f0 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1373,22 +1373,22 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, /* set pll power down */ writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), - pll->reg_base + RK3399_PLLCON(1)); + pll->reg_base + RK3588_PLLCON(1)); /* update pll values */ writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), - pll->reg_base + RK3399_PLLCON(0)); + pll->reg_base + RK3588_PLLCON(0)); writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), - pll->reg_base + RK3399_PLLCON(1)); + pll->reg_base + RK3588_PLLCON(1)); writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), - pll->reg_base + RK3399_PLLCON(2)); + pll->reg_base + RK3588_PLLCON(2)); /* set pll power up */ writel(HIWORD_UPDATE(0,