From c7fddf7117038435b6342d99cfa60d8efc7963a7 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 10 Nov 2021 21:11:39 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add opp table for gpu Signed-off-by: Finley Xiao Change-Id: I544f260410d9b5a17dfff2d1f6d30e55662cd812 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 7738956ed880..3187ded18909 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -796,10 +796,36 @@ clocks = <&cru CLK_GPU_COREGROUP>, <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>; clock-names = "clk_gpu_coregroup", "clk_gpu_stacks", "clk_gpu"; power-domains = <&power RK3588_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; status = "disabled"; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-198000000 { + opp-hz = /bits/ 64 <198000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + }; + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + }; + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + }; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + }; + }; + usbdrd3_0: usbdrd3_0 { compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,