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PCI: rockchip: dw: Move deassert #PERST after enabling LTSSM

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It was recommended by ECN document, so following it will make
less risk in probing devices in case the refclk is coming from
SoC.

Change-Id: Ic4514f373b6014c406d5436738419c64df6d32b2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2021-03-16 17:45:10 +08:00
committed by Tao Huang
parent 9a75da1582
commit c84a4aa411
1 changed files with 12 additions and 2 deletions
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14
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -445,8 +445,6 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
/* Rest the device */
gpiod_set_value_cansleep(rk_pcie->rst_gpio, 0);
msleep(1000);
gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
rk_pcie_disable_ltssm(rk_pcie);
rk_pcie_link_status_clear(rk_pcie);
@@ -455,6 +453,18 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
/* Enable LTSSM */
rk_pcie_enable_ltssm(rk_pcie);
/*
* PCIe requires the refclk to be stable for 100µs prior to releasing
* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
* Express Card Electromechanical Specification, 1.1. However, we don't
* know if the refclk is coming from RC's PHY or external OSC. If it's
* from RC, so enabling LTSSM is the just right place to release #PERST.
* We need a little more extra time as before, rather than setting just
* 100us as we don't know how long should the device need to reset.
*/
msleep(1000);
gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
for (retries = 0; retries < 10; retries++) {
if (dw_pcie_link_up(pci)) {
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",