From c86aa0a6b3cb7161235d0b2b8306502568a75f4e Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 6 May 2020 09:46:22 +0800 Subject: [PATCH] clk: rockchip: rk3368: use COMPOSITE_DCLK for dclk_vop Change-Id: I45ce9a2e404acb7eae885fbca0b4703ec67176e9 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3368.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index c6695b92a7e4..b4eb397a2214 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -15,6 +15,7 @@ #define RK3368_I2S_FRAC_MAX_PRATE 600000000 #define RK3368_UART_FRAC_MAX_PRATE 600000000 #define RK3368_SPDIF_FRAC_MAX_PRATE 600000000 +#define RK3368_DCLK_PARENT_MAX_PRATE 600000000 enum rk3368_plls { apllb, aplll, dpll, cpll, gpll, npll, @@ -469,9 +470,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT, + COMPOSITE_DCLK(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3368_CLKGATE_CON(4), 1, GFLAGS), + RK3368_CLKGATE_CON(4), 1, GFLAGS, RK3368_DCLK_PARENT_MAX_PRATE), GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0, RK3368_CLKGATE_CON(4), 2, GFLAGS),