shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/bridge: icn6211: Fix pll setting make the output clock freq more accurate

Browse Source 
Change-Id: Id8faa8677678cf187c3fadad7e5717315716f9da
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-05-29 15:39:24 +08:00
committed by Tao Huang
parent d3528bf2ff
commit c9aee8efb3
1 changed files with 6 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/bridge/icn6211.c
View File

@@ -362,23 +362,15 @@ static void icn6211_bridge_pre_enable(struct drm_bridge *bridge)
* FIXME:
* fout = fin / pll_refdiv / pll_extra_div * pll_int / pll_dv / 2
*/
pll_refdiv = 1;
pll_extra_div = 2;
if (mode->clock <= 44000) {
pll_dv = 8;
regmap_write(icn6211->regmap, PLL_REF_DIV, 0x71);
} else if (mode->clock <= 88000) {
pll_dv = 4;
regmap_write(icn6211->regmap, PLL_REF_DIV, 0x51);
} else {
pll_dv = 2;
regmap_write(icn6211->regmap, PLL_REF_DIV, 0x31);
}
pll_refdiv = 13;
pll_extra_div = 1;
pll_dv = 4;
regmap_write(icn6211->regmap, PLL_REF_DIV, 0x4d);
pll_int = DIV_ROUND_UP(mode->clock * 1000 * 2 * pll_dv,
refclk / pll_refdiv / pll_extra_div);
regmap_write(icn6211->regmap, PLL_INT_0, pll_int);
regmap_write(icn6211->regmap, PLL_INT_0, pll_int & 0xff);
regmap_write(icn6211->regmap, PLL_INT_1, (pll_int >> 8) & 0x3);
dev_dbg(icn6211->dev,
"pll_refdiv=%d, pll_extra_div=%d, pll_int=%d, pll_dv=%d\n",