From c9aee8efb3797ac63f574c85f34e5979b064f11b Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 29 May 2019 15:39:24 +0800 Subject: [PATCH] drm/bridge: icn6211: Fix pll setting make the output clock freq more accurate Change-Id: Id8faa8677678cf187c3fadad7e5717315716f9da Signed-off-by: Wyon Bi --- drivers/gpu/drm/bridge/icn6211.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/icn6211.c b/drivers/gpu/drm/bridge/icn6211.c index 96963766d1d3..db5f1e40b6cb 100644 --- a/drivers/gpu/drm/bridge/icn6211.c +++ b/drivers/gpu/drm/bridge/icn6211.c @@ -362,23 +362,15 @@ static void icn6211_bridge_pre_enable(struct drm_bridge *bridge) * FIXME: * fout = fin / pll_refdiv / pll_extra_div * pll_int / pll_dv / 2 */ - pll_refdiv = 1; - pll_extra_div = 2; - - if (mode->clock <= 44000) { - pll_dv = 8; - regmap_write(icn6211->regmap, PLL_REF_DIV, 0x71); - } else if (mode->clock <= 88000) { - pll_dv = 4; - regmap_write(icn6211->regmap, PLL_REF_DIV, 0x51); - } else { - pll_dv = 2; - regmap_write(icn6211->regmap, PLL_REF_DIV, 0x31); - } + pll_refdiv = 13; + pll_extra_div = 1; + pll_dv = 4; + regmap_write(icn6211->regmap, PLL_REF_DIV, 0x4d); pll_int = DIV_ROUND_UP(mode->clock * 1000 * 2 * pll_dv, refclk / pll_refdiv / pll_extra_div); - regmap_write(icn6211->regmap, PLL_INT_0, pll_int); + regmap_write(icn6211->regmap, PLL_INT_0, pll_int & 0xff); + regmap_write(icn6211->regmap, PLL_INT_1, (pll_int >> 8) & 0x3); dev_dbg(icn6211->dev, "pll_refdiv=%d, pll_extra_div=%d, pll_int=%d, pll_dv=%d\n",