diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 9b4f72503bdb..d28fe5728e7a 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -40,6 +40,7 @@ struct rockchip_combphy_grfcfg {
 	struct combphy_reg pipe_txcomp_set;
 	struct combphy_reg pipe_clk_25m;
 	struct combphy_reg pipe_clk_100m;
+	struct combphy_reg pipe_phymode_sel;
 	struct combphy_reg pipe_rate_sel;
 	struct combphy_reg pipe_rxterm_sel;
 	struct combphy_reg pipe_txelec_sel;
@@ -463,11 +464,13 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 		break;
 	case PHY_TYPE_SGMII:
 		param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
 		param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
 		param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
 		break;
 	case PHY_TYPE_QSGMII:
 		param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
 		param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
 		param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
 		param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
@@ -557,6 +560,7 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
 	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
 	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
 	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
 	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
 	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
 	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },