From cae7ca5fefb65ec90968d2eb713563c95495a689 Mon Sep 17 00:00:00 2001 From: Shunhua Lan Date: Wed, 2 Jun 2021 11:56:35 +0800 Subject: [PATCH] ARM: dts: rockchip: rk628: add i2s mclk config and select test_clkout pin as mclk output Signed-off-by: Shunhua Lan Change-Id: I32ef6ae68a0ffe6ac42a75de09d7995388815f03 --- arch/arm/boot/dts/rk628.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk628.dtsi b/arch/arm/boot/dts/rk628.dtsi index 47631dbbd23d..3a2f45c7ecfa 100644 --- a/arch/arm/boot/dts/rk628.dtsi +++ b/arch/arm/boot/dts/rk628.dtsi @@ -368,9 +368,12 @@ <&rk628_cru CGU_CLK_HDMIRX_CEC>, <&rk628_cru CGU_SCLK_VOP>, <&rk628_cru CGU_CLK_RX_READ>, - <&rk628_cru CGU_PCLK_CSI>; + <&rk628_cru CGU_PCLK_CSI>, + <&rk628_cru CGU_CLK_TESTOUT>; clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec", - "vop", "rx_read", "csi0"; + "vop", "rx_read", "csi0", "i2s_mclk"; + assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>; + assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>; resets = <&rk628_cru RGU_HDMIRX>, <&rk628_cru RGU_HDMIRX_PON>, <&rk628_cru RGU_DECODER>, @@ -382,7 +385,7 @@ phys = <&rk628_combrxphy>, <&rk628_combtxphy>; phy-names = "combrxphy", "combtxphy"; pinctrl-names = "default"; - pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins>; + pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>; status = "disabled"; }; };