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rk: add common efuse support
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@@ -21,6 +21,7 @@
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/hardirq.h>
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#include <plat/efuse.h>
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#include <mach/cru.h>
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#include <mach/iomux.h>
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#include <mach/clock.h>
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@@ -3411,43 +3412,6 @@ static void div_clk_for_pll_init(void)
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}
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/************************************for cpll runing checking****************************************/
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/* eFuse controller register */
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#define EFUSE_A_SHIFT (6)
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#define EFUSE_A_MASK (0xFF)
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//#define EFUSE_PD (1 << 5)
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//#define EFUSE_PS (1 << 4)
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#define EFUSE_PGENB (1 << 3)//active low
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#define EFUSE_LOAD (1 << 2)
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#define EFUSE_STROBE (1 << 1)
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#define EFUSE_CSB (1 << 0) //active low
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#define REG_EFUSE_CTRL (0x0000)
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#define REG_EFUSE_DOUT (0x0004)
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#define efuse_readl(offset) readl_relaxed(RK30_EFUSE_BASE + offset)
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#define efuse_writel(val, offset) writel_relaxed(val, RK30_EFUSE_BASE + offset)
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int efuse_readregs(u32 addr, u32 length, u8 *pData)
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{
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efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
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efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
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udelay(2);
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do {
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT), REG_EFUSE_CTRL);
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udelay(2);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_STROBE, REG_EFUSE_CTRL);
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udelay(2);
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*pData = efuse_readl(REG_EFUSE_DOUT);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~EFUSE_STROBE), REG_EFUSE_CTRL);
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udelay(2);
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pData++;
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addr++;
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} while(--length);
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udelay(2);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
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udelay(1);
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return 0;
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}
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static u8 pll_flag = 0;
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static int pll_get_flag(void)
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{
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@@ -12,6 +12,7 @@ obj-y += config.o
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obj-y += cpu.o
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obj-y += sram.o
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obj-y += iomux.o
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obj-y += efuse.o
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obj-$(CONFIG_DDR_TEST) += memtester.o ddr_test.o
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obj-$(CONFIG_DDR_FREQ) += ddr_freq.o
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obj-$(CONFIG_DVFS) += dvfs.o
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66
arch/arm/plat-rk/efuse.c
Normal file
66
arch/arm/plat-rk/efuse.c
Normal file
@@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2013 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <plat/efuse.h>
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/* eFuse controller register */
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#define EFUSE_A_SHIFT (6)
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#define EFUSE_A_MASK (0xFF)
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//#define EFUSE_PD (1 << 5)
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//#define EFUSE_PS (1 << 4)
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#define EFUSE_PGENB (1 << 3) //active low
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#define EFUSE_LOAD (1 << 2)
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#define EFUSE_STROBE (1 << 1)
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#define EFUSE_CSB (1 << 0) //active low
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#define REG_EFUSE_CTRL (0x0000)
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#define REG_EFUSE_DOUT (0x0004)
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#if defined(CONFIG_ARCH_RK3188)
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#define efuse_readl(offset) readl_relaxed(RK30_EFUSE_BASE + offset)
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#define efuse_writel(val, offset) writel_relaxed(val, RK30_EFUSE_BASE + offset)
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#endif
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int efuse_readregs(u32 addr, u32 length, u8 *pData)
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{
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#ifdef efuse_readl
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unsigned long flags;
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static DEFINE_SPINLOCK(efuse_lock);
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if (!length)
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return 0;
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spin_lock_irqsave(&efuse_lock, flags);
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efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
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efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
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udelay(2);
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do {
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT), REG_EFUSE_CTRL);
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udelay(2);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_STROBE, REG_EFUSE_CTRL);
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udelay(2);
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*pData = efuse_readl(REG_EFUSE_DOUT);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) & (~EFUSE_STROBE), REG_EFUSE_CTRL);
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udelay(2);
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pData++;
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addr++;
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} while(--length);
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udelay(2);
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efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
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udelay(1);
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spin_unlock_irqrestore(&efuse_lock, flags);
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#endif
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return 0;
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}
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8
arch/arm/plat-rk/include/plat/efuse.h
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8
arch/arm/plat-rk/include/plat/efuse.h
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@@ -0,0 +1,8 @@
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#ifndef __PLAT_EFUSE_H
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#define __PLAT_EFUSE_H
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#include <asm/types.h>
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int efuse_readregs(u32 addr, u32 length, u8 *pData);
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#endif
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