From cbd4930fdcd65bd21dc2621852a92d334e989d18 Mon Sep 17 00:00:00 2001 From: Hongjin Li Date: Thu, 26 Dec 2024 17:55:50 +0800 Subject: [PATCH] video: rockchip: mpp: rv1126b: code for support decoder decoder version: vdpu384a Change-Id: I784564a88de8687b9d211817d04794e10a4d104e Signed-off-by: Hongjin Li --- drivers/video/rockchip/mpp/mpp_rkvdec2.c | 66 +++++++++++++++++++ drivers/video/rockchip/mpp/mpp_rkvdec2_link.c | 60 +++++++++++++++++ drivers/video/rockchip/mpp/mpp_rkvdec2_link.h | 1 + 3 files changed, 127 insertions(+) diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2.c b/drivers/video/rockchip/mpp/mpp_rkvdec2.c index 216885100616..8eedea2da781 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2.c @@ -75,6 +75,18 @@ static struct mpp_hw_info rkvdec_vdpu383_hw_info = { .link_info = &rkvdec_link_vdpu383_hw_info, }; +static struct mpp_hw_info rkvdec_vdpu384a_hw_info = { + .reg_num = 296, + .reg_id = 0, + .reg_start = 0, + .reg_end = 295, + .reg_en = 16, + .reg_fmt = 8, + .reg_ret_status = 15, + .magic_base = 0x100, + .link_info = &rkvdec_link_vdpu384a_hw_info, +}; + /* * file handle translate information */ @@ -190,6 +202,46 @@ static struct mpp_trans_info rkvdec_vdpu383_trans[] = { } }; +/* + * file handle translate information + */ +static const u16 trans_vdpu384a_tbl_h265d[] = { + /* 128-135 general in/out */ + /* 140-160 rcb base */ + /* 168-185 dpb base */ + /* 192-210 payload */ + /* 216-232 colmv */ + 128, 129, 130, 131, 132, 133, 134, 135, 140, 142, 144, 146, 148, 150, 152, + 156, 158, 160, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, + 180, 181, 182, 183, 184, 185, 192, 194, 195, 196, 197, 198, 199, 200, 201, + 202, 203, 204, 205, 206, 207, 208, 209, 210, 216, 217, 218, 219, 220, 221, + 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232 +}; + +static const u16 trans_vdpu384a_tbl_h264d[] = { + /* 128-135 general in/out */ + /* 140-160 rcb base */ + /* 168-185 dpb base */ + /* 192-210 payload */ + /* 216-232 colmv */ + 128, 129, 130, 131, 132, 133, 134, 135, 140, 142, 144, 146, 148, 150, 152, + 156, 158, 160, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, + 180, 181, 182, 183, 184, 185, 192, 194, 195, 196, 197, 198, 199, 200, 201, + 202, 203, 204, 205, 206, 207, 208, 209, 210, 216, 217, 218, 219, 220, 221, + 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232 +}; + +static struct mpp_trans_info rkvdec_vdpu384a_trans[] = { + [RKVDEC_FMT_H265D] = { + .count = ARRAY_SIZE(trans_vdpu384a_tbl_h265d), + .table = trans_vdpu384a_tbl_h265d, + }, + [RKVDEC_FMT_H264D] = { + .count = ARRAY_SIZE(trans_vdpu384a_tbl_h264d), + .table = trans_vdpu384a_tbl_h264d, + }, +}; + static int mpp_extract_rcb_info(struct rkvdec2_rcb_info *rcb_inf, struct mpp_request *req) { @@ -1610,6 +1662,14 @@ static const struct mpp_dev_var rkvdec_rk3576_data = { .dev_ops = &rkvdec_vdpu383_dev_ops, }; +static const struct mpp_dev_var rkvdec_rv1126b_data = { + .device_type = MPP_DEVICE_RKVDEC, + .hw_info = &rkvdec_vdpu384a_hw_info, + .trans_info = rkvdec_vdpu384a_trans, + .hw_ops = &rkvdec_rk3576_hw_ops, + .dev_ops = &rkvdec_vdpu383_dev_ops, +}; + static const struct of_device_id mpp_rkvdec2_dt_match[] = { { .compatible = "rockchip,rkv-decoder-v2", @@ -1644,6 +1704,12 @@ static const struct of_device_id mpp_rkvdec2_dt_match[] = { .compatible = "rockchip,rkv-decoder-rk3576", .data = &rkvdec_rk3576_data, }, +#endif +#ifdef CONFIG_CPU_RV1126B + { + .compatible = "rockchip,rkv-decoder-rv1126b", + .data = &rkvdec_rv1126b_data, + }, #endif {}, }; diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c index e13bf2d55c04..e0cb86fb7be0 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c @@ -266,6 +266,66 @@ struct rkvdec_link_info rkvdec_link_vdpu383_hw_info = { .ip_en_val = 0x01000000, }; +/* vdpu384a link hw info */ +struct rkvdec_link_info rkvdec_link_vdpu384a_hw_info = { + .tb_reg_num = 256, + .tb_reg_next = 0, + .tb_reg_r = 1, + .tb_reg_second_en = -1, + .tb_reg_debug = 2, + .tb_reg_seg0 = 3, + .tb_reg_seg1 = 4, + .tb_reg_seg2 = 5, + + .part_w_num = 3, + .part_r_num = 2, + .part_w[0] = { + .tb_reg_off = 80, + .reg_start = 8, + .reg_num = 24, + }, + .part_w[1] = { + .tb_reg_off = 104, + .reg_start = 64, + .reg_num = 44, + }, + .part_w[2] = { + .tb_reg_off = 148, + .reg_start = 128, + .reg_num = 108, + }, + .part_r[0] = { + .tb_reg_off = 16, + .reg_start = 15, + .reg_num = 1, + }, + .part_r[1] = { + .tb_reg_off = 20, + .reg_start = 256, + .reg_num = 40, + }, + .tb_reg_int = 16, + .tb_reg_cycle = 27, + .reg_status = { + .dec_num_mask = 0x3fffffff, + .err_flag_base = 0x04c, + .err_flag_bit = 0x3fe, + }, + .next_addr_base = 0x20, + .ip_reset_base = 0x44, + .ip_reset_en = BIT(0), + .irq_base = 0x48, + .irq_mask = 0x30000, + .status_base = 0x4c, + .status_mask = 0x3ff0000, + .err_mask = 0x3fe, + .ip_reset_mask = 0x8000000, + .ip_time_base = 0x54, + .en_base = 0x40, + .ip_en_base = 0x58, + .ip_en_val = 0x01000000, +}; + static void rkvdec2_link_free_task(struct kref *ref); static void rkvdec2_link_timeout_proc(struct work_struct *work_s); static int rkvdec2_link_iommu_fault_handle(struct iommu_domain *iommu, diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h index ca6ae6acce0d..f391bddc223e 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h @@ -215,6 +215,7 @@ extern struct rkvdec_link_info rkvdec_link_rk356x_hw_info; extern struct rkvdec_link_info rkvdec_link_v2_hw_info; extern struct rkvdec_link_info rkvdec_link_vdpu382_hw_info; extern struct rkvdec_link_info rkvdec_link_vdpu383_hw_info; +extern struct rkvdec_link_info rkvdec_link_vdpu384a_hw_info; int rkvdec_link_dump(struct mpp_dev *mpp);