From cc03ee8220d1490e4c7de9014ced3c33aeef01d3 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 13 Nov 2017 15:32:25 +0800 Subject: [PATCH] clk: rockchip: rk3036: leave apll for core, mac and lcdc only In order not to affect other clocks, remove the apll from the parent list of other clocks and only core, mac and lcdc can select apll as parent. Change-Id: I58b995f8ccf69c6564f74b5823f618a186030d70 Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3036.c | 38 ++++++++++++++++--------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index dead0e6f2752..e11337993961 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -125,14 +125,16 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m", "xin24m" }; PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; -PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" }; +PNAME(mux_busclk_p) = { "dummy_apll", "dpll_cpu", "gpll_cpu" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; -PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; +PNAME(mux_pll_src_apll_dpll_gpll_p) = { "apll", "dpll", "gpll" }; +PNAME(mux_pll_src_dmyapll_dpll_gpll_p) = { "dummy_apll", "dpll", "gpll" }; + PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; -PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; +PNAME(mux_pll_src_dmyapll_dpll_gpll_usb480m_p) = { "dummy_apll", "dpll", "gpll", "usb480m" }; -PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; +PNAME(mux_mmc_src_p) = { "dummy_apll", "dpll", "gpll", "xin24m" }; PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" }; PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; @@ -217,7 +219,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 4, GFLAGS), - COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0, + COMPOSITE(0, "aclk_peri_src", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 0, GFLAGS), @@ -245,7 +247,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, RK2928_CLKGATE_CON(2), 5, GFLAGS), - MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, + MUX(0, "uart_pll_clk", mux_pll_src_dmyapll_dpll_gpll_usb480m_p, 0, RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0, RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, @@ -269,23 +271,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKGATE_CON(1), 13, GFLAGS, &rk3036_uart2_fracmux), - COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0, + COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, RK2928_CLKGATE_CON(3), 12, GFLAGS), - COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0, + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 6, GFLAGS), - COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0, + COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), - COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0, + COMPOSITE(0, "hclk_disp_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0, + COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_apll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), @@ -314,7 +316,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1), MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0), - COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0, + COMPOSITE(0, "i2s_src", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, @@ -327,7 +329,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(0), 14, GFLAGS), - COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0, + COMPOSITE(0, "spdif_src", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0, @@ -338,23 +340,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 5, GFLAGS), - COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0, + COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 13, GFLAGS), - COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0, + COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), - COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0, + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_dmyapll_dpll_gpll_p, 0, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, RK2928_CLKGATE_CON(10), 4, GFLAGS), - COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, + COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_usb480m_p, 0, RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT, + COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_apll_dpll_gpll_p, CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),