From cc761c9b6a310782b08f2c58f6d5941450e2827a Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 3 Nov 2021 09:08:59 +0800 Subject: [PATCH] arm64: dts: rockchip: add rk3588/rk3588s evb mipi panel info rk3588-evb1: dsi0->dphy->1080p_panel && dsi1->dphy->1080p_panel; rk3588-evb2: dsi1->dphy->1080p_panel; rk3588-evb3: dsi0->dphy->1080p_panel && dsi1->cphy->cphy_panel; rk3588-evb4: dsi0->dphy->1080p_panel; rk3588-evb5: dsi0->dcphy->test_connector && dsi1->dcphy->test_connector; rk3588s-evb1: dsi0->dphy->1080p_panel && dsi1->dphy->cmd_no_dsc_panel; rk3588s-evb2: dsi0->cphy->cphy_panel & dsi1->dphy->1080p_panel; rk3588s-evb3: dsi0->dcphy->test_connector && dsi1->dcphy->test_connector; rk3588s-evb4: dsi0->dphy->1080p_panel && dsi1->dphy->cmd_dsc_panel; Signed-off-by: Guochun Huang Change-Id: I4c03d8c351a605e643e4c61d3e388db09d1fa8be --- arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi | 712 +++++++++++++++++ .../boot/dts/rockchip/rk3588-evb1-lp4.dtsi | 81 ++ .../boot/dts/rockchip/rk3588-evb2-lp4.dtsi | 48 ++ .../boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 607 +++++++++++++++ .../boot/dts/rockchip/rk3588-evb4-lp4.dtsi | 47 ++ .../boot/dts/rockchip/rk3588-evb5-lp4.dtsi | 40 + arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi | 720 ++++++++++++++++++ .../boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi | 185 +++++ .../boot/dts/rockchip/rk3588s-evb2-lp5.dtsi | 606 +++++++++++++++ .../boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi | 40 + .../boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi | 180 +++++ 11 files changed, 3266 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi index fbe0a01378f5..a7f39471b174 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi @@ -44,6 +44,45 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + leds: leds { compatible = "gpio-leds"; work_led: work { @@ -83,6 +122,15 @@ regulator-max-microvolt = <12000000>; }; + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -114,6 +162,670 @@ }; }; +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + &i2s0_8ch { status = "okay"; rockchip,clk-trcm = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi index 6c0b5f16ca33..a34d815f9fb8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi @@ -108,6 +108,64 @@ }; }; +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + &i2c2 { status = "okay"; @@ -199,6 +257,14 @@ }; }; +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; @@ -212,6 +278,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -229,6 +301,10 @@ }; }; +&pwm2 { + status = "okay"; +}; + &u2phy1_otg { phy-supply = <&vcc5v0_host>; }; @@ -272,3 +348,8 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi index 7395779dc6f8..0ef533a689df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi @@ -112,6 +112,35 @@ }; }; +&backlight { + pwms = <&pwm3 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + &i2c2 { status = "okay"; @@ -163,6 +192,10 @@ }; }; +&mipi_dcphy1 { + status = "okay"; +}; + &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; @@ -180,6 +213,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + touch { touch_gpio: touch-gpio { rockchip,pins = @@ -195,6 +234,10 @@ }; }; +&pwm3 { + status = "okay"; +}; + &u2phy0_otg { phy-supply = <&vcc5v0_host>; }; @@ -210,3 +253,8 @@ &u2phy3_host { phy-supply = <&vcc5v0_host>; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi index f53fb5759a3e..e721c223eb53 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi @@ -125,6 +125,589 @@ }; }; +&backlight { + pwms = <&pwm15 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + phy-c-option; + dsi,lanes = <3>; + + panel-init-sequence = [ + 23 00 02 FF 20 + 23 00 02 FB 01 + 23 00 02 05 D9 + /* VGH=17V */ + 23 00 02 07 78 + /* VGL=-14V */ + 23 00 02 08 5A + /* EN_VMODGATE2=1 */ + 23 00 02 0D 63 + /* VGH=16V */ + 23 00 02 0E 91 + /* VGL=-13V */ + 23 00 02 0F 73 + /* GVDD=5.2V */ + 23 00 02 95 EB + 23 00 02 96 EB + /* Disable VDDI LV */ + 23 00 02 30 11 + /* ISOP */ + 23 00 02 6D 66 + /* EN_GMACP */ + 23 00 02 75 A2 + /* V128 */ + 23 00 02 77 3B + /* R(+) */ + 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* G(+) */ + 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* B(+) */ + 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* CMD2_Page1 */ + 23 00 02 FF 21 + 23 00 02 FB 01 + /* R(-) */ + 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* G(-) */ + 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* B(-) */ + 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + + 29 00 02 FF 24 + 29 00 02 FB 01 + /* VGL */ + 29 00 02 00 00 + 29 00 02 01 00 + /* VDDO */ + 29 00 02 02 1C + 29 00 02 03 1C + /* VDDE */ + 29 00 02 04 1D + 29 00 02 05 1D + /* STV0 */ + 29 00 02 06 04 + 29 00 02 07 04 + /* CLK8 */ + 29 00 02 08 0F + 29 00 02 09 0F + /* CLK6 */ + 29 00 02 0A 0E + 29 00 02 0B 0E + /* CLK4 */ + 29 00 02 0C 0D + 29 00 02 0D 0D + /* CLK2 */ + 29 00 02 0E 0C + 29 00 02 0F 0C + /* STV2 */ + 29 00 02 10 08 + 29 00 02 11 08 + + 29 00 02 12 00 + 29 00 02 13 00 + 29 00 02 14 00 + 29 00 02 15 00 + /* VGL */ + 29 00 02 16 00 + 29 00 02 17 00 + /* VDDO */ + 29 00 02 18 1C + 29 00 02 19 1C + /* VDDE */ + 29 00 02 1A 1D + 29 00 02 1B 1D + /* STV0 */ + 29 00 02 1C 04 + 29 00 02 1D 04 + /* CLK7 */ + 29 00 02 1E 0F + 29 00 02 1F 0F + /* CLK5 */ + 29 00 02 20 0E + 29 00 02 21 0E + /* CLK3 */ + 29 00 02 22 0D + 29 00 02 23 0D + /* CLK1 */ + 29 00 02 24 0C + 29 00 02 25 0C + /* STV1 */ + 29 00 02 26 08 + 29 00 02 27 08 + + 29 00 02 28 00 + 29 00 02 29 00 + 29 00 02 2A 00 + 29 00 02 2B 00 + /* STV0 */ + 29 00 02 2D 20 + 29 00 02 2F 0A + 29 00 02 30 44 + 29 00 02 33 0C + 29 00 02 34 32 + + 29 00 02 37 44 + 29 00 02 38 40 + 29 00 02 39 00 + 29 00 02 3A 50 + 29 00 02 3B 50 + 29 00 02 3D 42 + /* STV */ + 29 00 02 3F 06 + 29 00 02 43 06 + + 29 00 02 47 66 + 29 00 02 4A 50 + 29 00 02 4B 50 + 29 00 02 4C 91 + /* GCK */ + 29 00 02 4D 21 + 29 00 02 4E 43 + 29 00 02 51 12 + 29 00 02 52 34 + 29 00 03 55 82 02 + 29 00 02 56 04 + 29 00 02 58 21 + 29 00 02 59 30 + 29 00 02 5A 50 + 29 00 02 5B 50 + 29 00 03 5E 00 06 + 29 00 02 5F 00 + /* EN_LFD_SOURCE=0 */ + 29 00 02 65 82 + /* VDDO, VDDE */ + 29 00 02 7E 20 + 29 00 02 7F 3C + 29 00 02 82 04 + 29 00 02 97 C0 + + 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 + /* qclk=96/5 Mhz */ + 29 00 02 91 44 + 29 00 02 92 55 + 29 00 02 93 1A + 29 00 02 94 5F + /* SOG_HBP */ + 29 00 02 D7 55 + 29 00 02 DA 0A + 29 00 02 DE 08 + /* Normal */ + 29 00 02 DB 05 + 29 00 02 DC 55 + 29 00 02 DD 22 + /* Line N */ + 29 00 02 DF 05 + 29 00 02 E0 55 + /* Line N+1 */ + 29 00 02 E1 05 + 29 00 02 E2 55 + /* TP0 */ + 29 00 02 E3 05 + 29 00 02 E4 55 + /* TP3 */ + 29 00 02 E5 05 + 29 00 02 E6 55 + /* Gate EQ */ + 29 00 02 5C 00 + 29 00 02 5D 00 + /* TP3 */ + 29 00 02 8D 00 + 29 00 02 8E 00 + /* No Sync @ TP */ + 29 00 02 B5 90 + + 29 00 02 FF 25 + 29 00 02 FB 01 + /* disable auto_vbp_vfp */ + 29 00 02 05 00 + /* ESD_DET_ERR_SEL */ + 29 00 02 19 07 + /* DP_N_GCK */ + 29 00 02 1F 50 + 29 00 02 20 50 + /* DP_N_1_GCK */ + 29 00 02 26 50 + 29 00 02 27 50 + /* TP0_GCK */ + 29 00 02 33 50 + 29 00 02 34 50 + /* TP3 GCK/MUX=1 */ + 29 00 02 3F E0 + /* TP3_GCK_START_LINE */ + 29 00 02 40 00 + /* TP3_STV */ + 29 00 02 44 00 + 29 00 02 45 40 + /* TP3_GCK */ + 29 00 02 48 50 + 29 00 02 49 50 + /* LSTP0 */ + 29 00 02 5B 00 + 29 00 02 5C 00 + 29 00 02 5D 00 + 29 00 02 5E D0 + + 29 00 02 61 50 + 29 00 02 62 50 + /* en_vfp_addvsync */ + 29 00 02 F1 10 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + /* PWRONOFF */ + /* STV */ + 29 00 02 64 16 + /* CLR */ + 29 00 02 67 16 + /* GCK */ + 29 00 02 6A 16 + /* POL */ + 29 00 02 70 30 + /* ABOFF */ + 29 00 02 A2 F3 + 29 00 02 A3 FF + 29 00 02 A4 FF + 29 00 02 A5 FF + /* Long_V_TIMING disable */ + 29 00 02 D6 08 + /* CMD2,Page6 */ + 29 00 02 FF 26 + 29 00 02 FB 01 + /* TPEN */ + 29 00 02 00 81 + /* 90Hz */ + 29 00 02 01 30 + + 29 00 02 02 31 + 29 00 02 0A F2 + //Table A (90Hz) + 29 00 02 04 28 + 29 00 02 06 3C + 29 00 02 0C 0B + 29 00 02 0D 0C + 29 00 02 0F 00 + 29 00 02 11 00 + 29 00 02 12 50 + 29 00 02 13 AE + 29 00 02 14 A6 + 29 00 02 16 10 + 29 00 02 19 08 + 29 00 02 1A FF + 29 00 02 1B 08 + 29 00 02 1C 80 + 29 00 02 22 00 + 29 00 02 23 00 + 29 00 02 2A 08 + 29 00 02 2B FF + + 29 00 02 1D 00 + 29 00 02 1E 55 + 29 00 02 1F 55 + 29 00 02 24 00 + 29 00 02 25 55 + 29 00 02 2F 05 + 29 00 02 30 55 + 29 00 02 31 05 + 29 00 02 32 6D + 29 00 02 39 00 + 29 00 02 3A 55 + /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ + 29 00 02 8B 28 + 29 00 02 8C 13 + 29 00 02 8D 0A + 29 00 02 8F 0A + 29 00 02 91 00 + 29 00 02 92 50 + 29 00 02 93 51 + 29 00 02 94 65 + 29 00 02 96 10 + 29 00 02 99 0A + 29 00 02 9A 7F + 29 00 02 9B 0A + 29 00 02 9C 0C + 29 00 02 9D 0A + 29 00 02 9E 7F + + 29 00 02 3F 00 + 29 00 02 40 75 + 29 00 02 41 75 + 29 00 02 42 75 + 29 00 02 43 00 + 29 00 02 44 75 + 29 00 02 45 05 + 29 00 02 46 75 + 29 00 02 47 05 + 29 00 02 48 8D + 29 00 02 49 00 + 29 00 02 4A 75 + /* STV0 */ + 29 00 02 4D 5D + 29 00 02 4E 60 + /* STV */ + 29 00 02 4F 5D + 29 00 02 50 60 + /* GCK */ + 29 00 02 51 70 + 29 00 02 52 60 + /* DP_N_GCK */ + 29 00 02 56 70 + 29 00 02 58 60 + /* DP_N_1_GCK */ + 29 00 02 5B 70 + 29 00 02 5C 60 + /* TP0_GCK */ + 29 00 02 60 70 + 29 00 02 61 60 + /* TP3_GCK */ + 29 00 02 64 70 + 29 00 02 65 60 + /* LSTP0 */ + 29 00 02 72 70 + 29 00 02 73 60 + /* PRZ1 */ + 29 00 02 20 01 + /* PRZ3 */ + /* Rescan=3 */ + 29 00 02 33 11 + 29 00 02 34 78 + 29 00 02 35 16 + /* DLH */ + 29 00 02 C8 04 + 29 00 02 C9 80 + 29 00 02 CA 4E + 29 00 02 CB 00 + 29 00 02 A9 4C + 29 00 02 AA 47 + /* CMD2,Page7 */ + 29 00 02 FF 27 + 29 00 02 FB 01 + /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ + 29 00 02 56 06 + /* FR0(60Hz) */ + 29 00 02 58 80 + 29 00 02 59 53 + 29 00 02 5A 00 + 29 00 02 5B 14 + 29 00 02 5C 00 + 29 00 02 5D 01 + 29 00 02 5E 20 + 29 00 02 5F 10 + 29 00 02 60 00 + 29 00 02 61 1D + 29 00 02 62 00 + 29 00 02 63 01 + 29 00 02 64 24 + 29 00 02 65 1C + 29 00 02 66 00 + 29 00 02 67 01 + 29 00 02 68 25 + /* FR1(90Hz) */ + 29 00 02 78 80 + 29 00 02 79 73 + 29 00 02 7A 00 + 29 00 02 7B 14 + 29 00 02 7C 00 + 29 00 02 7D 02 + 29 00 02 7E 20 + 29 00 02 7F 21 + 29 00 02 80 00 + 29 00 02 81 2A + 29 00 02 82 00 + 29 00 02 83 01 + 29 00 02 84 1C + 29 00 02 85 28 + 29 00 02 86 00 + 29 00 02 87 01 + 29 00 02 88 1D + + 29 00 02 00 00 + 29 00 02 C3 00 + /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ + 29 00 02 D1 24 + 29 00 02 D2 53 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + 29 00 02 01 05 + 29 00 02 02 55 + /* TP0 */ + 29 00 02 03 05 + 29 00 02 04 75 + /* TP3 */ + 29 00 02 05 05 + 29 00 02 06 75 + /* PEN_EN=1, UL_FREQ=0 */ + 29 00 02 22 2F + /* 90Hz */ + 29 00 02 23 11 + /* FR0 (60Hz) */ + 29 00 02 24 00 + 29 00 02 25 75 + 29 00 02 27 00 + 29 00 02 28 1A + 29 00 02 29 00 + 29 00 02 2A 1A + 29 00 02 2B 00 + 29 00 02 2D 1A + /* FR1 (90Hz) */ + 29 00 02 2F 00 + 29 00 02 30 55 + 29 00 02 32 00 + 29 00 02 33 1A + 29 00 02 34 00 + 29 00 02 35 1A + 29 00 02 36 00 + 29 00 02 37 1A + /* CMD2,Page3 */ + 29 00 02 FF 23 + 29 00 02 FB 01 + /* DBV=12 bit */ + 29 00 02 00 80 + /* PWM frequency */ + 29 00 02 07 00 + /* CMD3,PageA */ + 29 00 02 FF E0 + 29 00 02 FB 01 + /* VCOM Driving Ability */ + 29 00 02 14 60 + 29 00 02 16 C0 + /* CMD3,PageB */ + 29 00 02 FF F0 + 29 00 02 FB 01 + /* slave osc workaround */ + 29 00 02 3A 08 + /* CMD3,PageC */ + 29 00 02 FF D0 + 29 00 02 FB 01 + 29 00 02 1C 88 + 29 00 02 1D 08 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Only Write Slave */ + 29 00 02 B9 01 + /* CMD2,Page0 */ + 29 00 02 FF 20 + 29 00 02 FB 01 + 29 00 02 18 40 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Write Master & Slave */ + 29 00 02 B9 02 + 29 00 02 35 00 + 29 00 03 51 00 FF + 29 00 02 53 24 + 29 00 02 55 00 + 29 00 02 BB 13 + /* VBP+VFP=121 */ + 29 00 06 3B 03 5F 1A 04 04 + /* CMD2,Page5 */ + 29 00 02 FF 25 + /* FRM */ + 29 00 02 EC 00 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + 05 FF 01 11 + 05 FF 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <241300000>; + hactive = <1200>; + vactive = <2000>; + hfront-porch = <31>; + hsync-len = <1>; + hback-porch = <32>; + vfront-porch = <26>; + vsync-len = <2>; + vback-porch = <93>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + &i2c2 { status = "okay"; @@ -227,6 +810,15 @@ }; }; +&mipi_dcphy0 { + status = "okay"; +}; + + +&mipi_dcphy1 { + status = "disabled"; +}; + &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; @@ -244,6 +836,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + touch { touch_gpio: touch-gpio { rockchip,pins = @@ -269,6 +867,10 @@ }; }; +&pwm15 { + status = "okay"; +}; + &u2phy1_otg { phy-supply = <&vcc5v0_host>; }; @@ -312,3 +914,8 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi index 06c6b34dd02e..6fe4fd47524f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi @@ -64,6 +64,34 @@ }; }; +&backlight { + pwms = <&pwm3 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + &i2c6 { status = "okay"; gt1x: gt1x@14 { @@ -130,6 +158,10 @@ }; }; +&mipi_dcphy0 { + status = "okay"; +}; + &pcie3x4 { compatible = "rockchip,rk3588-pcie-ep"; memory-region = <&dma_trans>; @@ -137,6 +169,12 @@ }; &pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + touch { touch_gpio: touch-gpio { rockchip,pins = @@ -162,6 +200,10 @@ }; }; +&pwm3 { + status = "okay"; +}; + &u2phy2 { status = "disabled"; }; @@ -229,3 +271,8 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi index 0e6953f107a6..5d5d502612f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi @@ -76,6 +76,38 @@ status = "okay"; }; +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + &i2c6 { status = "okay"; gt1x: gt1x@14 { @@ -94,6 +126,14 @@ /delete-property/ pinctrl-0; }; +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi index d2142dd962ab..f293a8650eab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi @@ -44,6 +44,53 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + test-power { status = "okay"; }; @@ -75,6 +122,15 @@ regulator-max-microvolt = <12000000>; }; + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -123,6 +179,670 @@ }; }; +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + &saradc { status = "okay"; vref-supply = <&vcc_1v8_s0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi index 92e50bca1b77..b14764af4e51 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi @@ -107,6 +107,168 @@ }; }; +&backlight { + pwms = <&pwm13 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + slice-width = <720>; + slice-height = <65>; + version-major = <1>; + version-minor = <1>; + + panel-init-sequence = [ + 29 10 03 f0 5a 5a + /* + * DSC Setting + * Compression Enable + */ + 07 10 01 00 + /* Scaler Enable x4 */ + 15 10 02 c3 11 + /* PPS Setting */ + 0a 31 58 11 00 00 89 30 80 06 18 02 d0 00 34 01 68 01 68 02 00 01 b4 00 20 04 04 00 05 00 0C 01 e2 02 ef 18 00 10 F0 03 0C 20 00 06 0B 0B 33 0E 1C 2A 38 46 54 62 69 70 77 79 7B 7D 7E 01 02 01 00 09 40 09 BE 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 2A F6 2B 34 2B 74 3B 74 6B F4 + 29 10 03 f0 a5 a5 + /* Sleep Out */ + 05 00 01 11 + /* 4 Common Setting */ + /* 4.1 TE(Vync) ON/OFF */ + 15 00 02 35 00 + /* 4.2 CASET/PASET Setting */ + 39 00 05 2a 00 00 02 cf + 39 00 05 2b 00 00 06 17 + /* 4.3 TSP SYNC Setting */ + 39 00 03 f0 5a 5a + 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 + 39 00 03 f0 a5 a5 + /* FD(Fast Discharge) Setting */ + 39 00 03 F0 5A 5A + 15 00 02 b0 45 + 15 00 02 b5 48 + 39 00 03 F0 A5 A5 + /* 4.6 FFC Setting (MIPI CLK 529MHz) */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 1E + 39 00 06 c5 09 10 b4 24 fb + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* OSC Spread Setting */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 37 + 39 00 06 c5 04 ff 00 01 64 + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* Memory access & Image Data Write(2Ch/3Ch) */ + /* Dither IP Setting */ + 39 00 03 fc 5a 5a + 15 00 02 b0 b6 + 15 00 02 eb 01 + 39 00 03 fc a5 a5 + /* 5 Brightness Control */ + /* 5.1 Dimming Setting */ + 39 10 03 f0 5a 5a + 23 10 02 b0 05 + 23 10 02 b1 01 + 23 10 02 b0 02 + 15 10 02 b5 d3 + 15 10 02 53 20 + 39 10 03 f0 a5 a5 + 39 10 03 51 02 ff + /* Scaler Enable x4 */ + 15 10 02 c3 11 + /* Display On */ + 05 78 01 11 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + /* Display Off */ + 05 14 01 28 + /* Sleep In */ + 05 00 01 10 + /* VCI stabilization Setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 05 + 15 00 02 f4 01 + 39 a0 03 f0 a5 a5 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <72000000>; + hactive = <720>; + vactive = <1560>; + hfront-porch = <10>; + hsync-len = <10>; + hback-porch = <10>; + vfront-porch = <10>; + vsync-len = <10>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + &i2c3 { status = "okay"; @@ -249,6 +411,14 @@ }; }; +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie20>; @@ -271,6 +441,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + mpu6500 { mpu6500_irq_gpio: mpu6500-irq-gpio { rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; @@ -302,6 +478,10 @@ }; }; +&pwm13 { + status = "okay"; +}; + &spdif_tx1 { status = "okay"; pinctrl-names = "default"; @@ -355,3 +535,8 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi index acb1a1beb7df..e1139e16b53c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi @@ -91,6 +91,589 @@ }; }; +&backlight { + pwms = <&pwm7 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi0 enable and dsi1 disabled + * case. + */ + //reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + phy-c-option; + dsi,lanes = <3>; + + panel-init-sequence = [ + 23 00 02 FF 20 + 23 00 02 FB 01 + 23 00 02 05 D9 + /* VGH=17V */ + 23 00 02 07 78 + /* VGL=-14V */ + 23 00 02 08 5A + /* EN_VMODGATE2=1 */ + 23 00 02 0D 63 + /* VGH=16V */ + 23 00 02 0E 91 + /* VGL=-13V */ + 23 00 02 0F 73 + /* GVDD=5.2V */ + 23 00 02 95 EB + 23 00 02 96 EB + /* Disable VDDI LV */ + 23 00 02 30 11 + /* ISOP */ + 23 00 02 6D 66 + /* EN_GMACP */ + 23 00 02 75 A2 + /* V128 */ + 23 00 02 77 3B + /* R(+) */ + 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* G(+) */ + 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* B(+) */ + 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* CMD2_Page1 */ + 23 00 02 FF 21 + 23 00 02 FB 01 + /* R(-) */ + 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* G(-) */ + 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* B(-) */ + 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + + 29 00 02 FF 24 + 29 00 02 FB 01 + /* VGL */ + 29 00 02 00 00 + 29 00 02 01 00 + /* VDDO */ + 29 00 02 02 1C + 29 00 02 03 1C + /* VDDE */ + 29 00 02 04 1D + 29 00 02 05 1D + /* STV0 */ + 29 00 02 06 04 + 29 00 02 07 04 + /* CLK8 */ + 29 00 02 08 0F + 29 00 02 09 0F + /* CLK6 */ + 29 00 02 0A 0E + 29 00 02 0B 0E + /* CLK4 */ + 29 00 02 0C 0D + 29 00 02 0D 0D + /* CLK2 */ + 29 00 02 0E 0C + 29 00 02 0F 0C + /* STV2 */ + 29 00 02 10 08 + 29 00 02 11 08 + + 29 00 02 12 00 + 29 00 02 13 00 + 29 00 02 14 00 + 29 00 02 15 00 + /* VGL */ + 29 00 02 16 00 + 29 00 02 17 00 + /* VDDO */ + 29 00 02 18 1C + 29 00 02 19 1C + /* VDDE */ + 29 00 02 1A 1D + 29 00 02 1B 1D + /* STV0 */ + 29 00 02 1C 04 + 29 00 02 1D 04 + /* CLK7 */ + 29 00 02 1E 0F + 29 00 02 1F 0F + /* CLK5 */ + 29 00 02 20 0E + 29 00 02 21 0E + /* CLK3 */ + 29 00 02 22 0D + 29 00 02 23 0D + /* CLK1 */ + 29 00 02 24 0C + 29 00 02 25 0C + /* STV1 */ + 29 00 02 26 08 + 29 00 02 27 08 + + 29 00 02 28 00 + 29 00 02 29 00 + 29 00 02 2A 00 + 29 00 02 2B 00 + /* STV0 */ + 29 00 02 2D 20 + 29 00 02 2F 0A + 29 00 02 30 44 + 29 00 02 33 0C + 29 00 02 34 32 + + 29 00 02 37 44 + 29 00 02 38 40 + 29 00 02 39 00 + 29 00 02 3A 50 + 29 00 02 3B 50 + 29 00 02 3D 42 + /* STV */ + 29 00 02 3F 06 + 29 00 02 43 06 + + 29 00 02 47 66 + 29 00 02 4A 50 + 29 00 02 4B 50 + 29 00 02 4C 91 + /* GCK */ + 29 00 02 4D 21 + 29 00 02 4E 43 + 29 00 02 51 12 + 29 00 02 52 34 + 29 00 03 55 82 02 + 29 00 02 56 04 + 29 00 02 58 21 + 29 00 02 59 30 + 29 00 02 5A 50 + 29 00 02 5B 50 + 29 00 03 5E 00 06 + 29 00 02 5F 00 + /* EN_LFD_SOURCE=0 */ + 29 00 02 65 82 + /* VDDO, VDDE */ + 29 00 02 7E 20 + 29 00 02 7F 3C + 29 00 02 82 04 + 29 00 02 97 C0 + + 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 + /* qclk=96/5 Mhz */ + 29 00 02 91 44 + 29 00 02 92 55 + 29 00 02 93 1A + 29 00 02 94 5F + /* SOG_HBP */ + 29 00 02 D7 55 + 29 00 02 DA 0A + 29 00 02 DE 08 + /* Normal */ + 29 00 02 DB 05 + 29 00 02 DC 55 + 29 00 02 DD 22 + /* Line N */ + 29 00 02 DF 05 + 29 00 02 E0 55 + /* Line N+1 */ + 29 00 02 E1 05 + 29 00 02 E2 55 + /* TP0 */ + 29 00 02 E3 05 + 29 00 02 E4 55 + /* TP3 */ + 29 00 02 E5 05 + 29 00 02 E6 55 + /* Gate EQ */ + 29 00 02 5C 00 + 29 00 02 5D 00 + /* TP3 */ + 29 00 02 8D 00 + 29 00 02 8E 00 + /* No Sync @ TP */ + 29 00 02 B5 90 + + 29 00 02 FF 25 + 29 00 02 FB 01 + /* disable auto_vbp_vfp */ + 29 00 02 05 00 + /* ESD_DET_ERR_SEL */ + 29 00 02 19 07 + /* DP_N_GCK */ + 29 00 02 1F 50 + 29 00 02 20 50 + /* DP_N_1_GCK */ + 29 00 02 26 50 + 29 00 02 27 50 + /* TP0_GCK */ + 29 00 02 33 50 + 29 00 02 34 50 + /* TP3 GCK/MUX=1 */ + 29 00 02 3F E0 + /* TP3_GCK_START_LINE */ + 29 00 02 40 00 + /* TP3_STV */ + 29 00 02 44 00 + 29 00 02 45 40 + /* TP3_GCK */ + 29 00 02 48 50 + 29 00 02 49 50 + /* LSTP0 */ + 29 00 02 5B 00 + 29 00 02 5C 00 + 29 00 02 5D 00 + 29 00 02 5E D0 + + 29 00 02 61 50 + 29 00 02 62 50 + /* en_vfp_addvsync */ + 29 00 02 F1 10 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + /* PWRONOFF */ + /* STV */ + 29 00 02 64 16 + /* CLR */ + 29 00 02 67 16 + /* GCK */ + 29 00 02 6A 16 + /* POL */ + 29 00 02 70 30 + /* ABOFF */ + 29 00 02 A2 F3 + 29 00 02 A3 FF + 29 00 02 A4 FF + 29 00 02 A5 FF + /* Long_V_TIMING disable */ + 29 00 02 D6 08 + /* CMD2,Page6 */ + 29 00 02 FF 26 + 29 00 02 FB 01 + /* TPEN */ + 29 00 02 00 81 + /* 90Hz */ + 29 00 02 01 30 + + 29 00 02 02 31 + 29 00 02 0A F2 + //Table A (90Hz) + 29 00 02 04 28 + 29 00 02 06 3C + 29 00 02 0C 0B + 29 00 02 0D 0C + 29 00 02 0F 00 + 29 00 02 11 00 + 29 00 02 12 50 + 29 00 02 13 AE + 29 00 02 14 A6 + 29 00 02 16 10 + 29 00 02 19 08 + 29 00 02 1A FF + 29 00 02 1B 08 + 29 00 02 1C 80 + 29 00 02 22 00 + 29 00 02 23 00 + 29 00 02 2A 08 + 29 00 02 2B FF + + 29 00 02 1D 00 + 29 00 02 1E 55 + 29 00 02 1F 55 + 29 00 02 24 00 + 29 00 02 25 55 + 29 00 02 2F 05 + 29 00 02 30 55 + 29 00 02 31 05 + 29 00 02 32 6D + 29 00 02 39 00 + 29 00 02 3A 55 + /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ + 29 00 02 8B 28 + 29 00 02 8C 13 + 29 00 02 8D 0A + 29 00 02 8F 0A + 29 00 02 91 00 + 29 00 02 92 50 + 29 00 02 93 51 + 29 00 02 94 65 + 29 00 02 96 10 + 29 00 02 99 0A + 29 00 02 9A 7F + 29 00 02 9B 0A + 29 00 02 9C 0C + 29 00 02 9D 0A + 29 00 02 9E 7F + + 29 00 02 3F 00 + 29 00 02 40 75 + 29 00 02 41 75 + 29 00 02 42 75 + 29 00 02 43 00 + 29 00 02 44 75 + 29 00 02 45 05 + 29 00 02 46 75 + 29 00 02 47 05 + 29 00 02 48 8D + 29 00 02 49 00 + 29 00 02 4A 75 + /* STV0 */ + 29 00 02 4D 5D + 29 00 02 4E 60 + /* STV */ + 29 00 02 4F 5D + 29 00 02 50 60 + /* GCK */ + 29 00 02 51 70 + 29 00 02 52 60 + /* DP_N_GCK */ + 29 00 02 56 70 + 29 00 02 58 60 + /* DP_N_1_GCK */ + 29 00 02 5B 70 + 29 00 02 5C 60 + /* TP0_GCK */ + 29 00 02 60 70 + 29 00 02 61 60 + /* TP3_GCK */ + 29 00 02 64 70 + 29 00 02 65 60 + /* LSTP0 */ + 29 00 02 72 70 + 29 00 02 73 60 + /* PRZ1 */ + 29 00 02 20 01 + /* PRZ3 */ + /* Rescan=3 */ + 29 00 02 33 11 + 29 00 02 34 78 + 29 00 02 35 16 + /* DLH */ + 29 00 02 C8 04 + 29 00 02 C9 80 + 29 00 02 CA 4E + 29 00 02 CB 00 + 29 00 02 A9 4C + 29 00 02 AA 47 + /* CMD2,Page7 */ + 29 00 02 FF 27 + 29 00 02 FB 01 + /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ + 29 00 02 56 06 + /* FR0(60Hz) */ + 29 00 02 58 80 + 29 00 02 59 53 + 29 00 02 5A 00 + 29 00 02 5B 14 + 29 00 02 5C 00 + 29 00 02 5D 01 + 29 00 02 5E 20 + 29 00 02 5F 10 + 29 00 02 60 00 + 29 00 02 61 1D + 29 00 02 62 00 + 29 00 02 63 01 + 29 00 02 64 24 + 29 00 02 65 1C + 29 00 02 66 00 + 29 00 02 67 01 + 29 00 02 68 25 + /* FR1(90Hz) */ + 29 00 02 78 80 + 29 00 02 79 73 + 29 00 02 7A 00 + 29 00 02 7B 14 + 29 00 02 7C 00 + 29 00 02 7D 02 + 29 00 02 7E 20 + 29 00 02 7F 21 + 29 00 02 80 00 + 29 00 02 81 2A + 29 00 02 82 00 + 29 00 02 83 01 + 29 00 02 84 1C + 29 00 02 85 28 + 29 00 02 86 00 + 29 00 02 87 01 + 29 00 02 88 1D + + 29 00 02 00 00 + 29 00 02 C3 00 + /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ + 29 00 02 D1 24 + 29 00 02 D2 53 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + 29 00 02 01 05 + 29 00 02 02 55 + /* TP0 */ + 29 00 02 03 05 + 29 00 02 04 75 + /* TP3 */ + 29 00 02 05 05 + 29 00 02 06 75 + /* PEN_EN=1, UL_FREQ=0 */ + 29 00 02 22 2F + /* 90Hz */ + 29 00 02 23 11 + /* FR0 (60Hz) */ + 29 00 02 24 00 + 29 00 02 25 75 + 29 00 02 27 00 + 29 00 02 28 1A + 29 00 02 29 00 + 29 00 02 2A 1A + 29 00 02 2B 00 + 29 00 02 2D 1A + /* FR1 (90Hz) */ + 29 00 02 2F 00 + 29 00 02 30 55 + 29 00 02 32 00 + 29 00 02 33 1A + 29 00 02 34 00 + 29 00 02 35 1A + 29 00 02 36 00 + 29 00 02 37 1A + /* CMD2,Page3 */ + 29 00 02 FF 23 + 29 00 02 FB 01 + /* DBV=12 bit */ + 29 00 02 00 80 + /* PWM frequency */ + 29 00 02 07 00 + /* CMD3,PageA */ + 29 00 02 FF E0 + 29 00 02 FB 01 + /* VCOM Driving Ability */ + 29 00 02 14 60 + 29 00 02 16 C0 + /* CMD3,PageB */ + 29 00 02 FF F0 + 29 00 02 FB 01 + /* slave osc workaround */ + 29 00 02 3A 08 + /* CMD3,PageC */ + 29 00 02 FF D0 + 29 00 02 FB 01 + 29 00 02 1C 88 + 29 00 02 1D 08 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Only Write Slave */ + 29 00 02 B9 01 + /* CMD2,Page0 */ + 29 00 02 FF 20 + 29 00 02 FB 01 + 29 00 02 18 40 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Write Master & Slave */ + 29 00 02 B9 02 + 29 00 02 35 00 + 29 00 03 51 00 FF + 29 00 02 53 24 + 29 00 02 55 00 + 29 00 02 BB 13 + /* VBP+VFP=121 */ + 29 00 06 3B 03 5F 1A 04 04 + /* CMD2,Page5 */ + 29 00 02 FF 25 + /* FRM */ + 29 00 02 EC 00 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + 05 FF 01 11 + 05 FF 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <241300000>; + hactive = <1200>; + vactive = <2000>; + hfront-porch = <31>; + hsync-len = <1>; + hback-porch = <32>; + vfront-porch = <26>; + vsync-len = <2>; + vback-porch = <93>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + &i2c2 { status = "okay"; @@ -145,6 +728,14 @@ }; }; +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + &sdmmc { status = "okay"; }; @@ -160,6 +751,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + touch { touch_gpio: touch-gpio { rockchip,pins = @@ -183,6 +780,10 @@ }; }; +&pwm7 { + status = "okay"; +}; + &u2phy0_otg { vbus-supply = <&vbus5v0_typec>; }; @@ -198,3 +799,8 @@ &usbdrd_dwc3_0 { maximum-speed = "high-speed"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi index c24f1cdef313..e7f5456a89c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi @@ -52,6 +52,38 @@ }; }; +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + &i2c2 { status = "okay"; @@ -137,6 +169,14 @@ }; }; +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + &sdmmc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi index 9c7e811013f1..db7cc9c424a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi @@ -107,6 +107,163 @@ }; }; +&backlight { + pwms = <&pwm13 0 25000 0>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + //rockchip,lane-rate = <650>; + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + compressed-data; + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + slice-width = <720>; + slice-height = <65>; + version-major = <1>; + version-minor = <1>; + + panel-init-sequence = [ + 29 10 03 f0 5a 5a + /* Dsc Setting */ + /* Compression Enable */ + 07 10 01 01 + /* Scaler Disable */ + 15 10 02 c3 00 + /* PPS Setting */ + 0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00 + 29 10 03 f0 a5 a5 + /** Sleep Out */ + 05 00 01 11 + /* 4. Common Setting */ + /* 4.1 TE(Vync) ON/OFF */ + 15 00 02 35 00 + /* 4.2 CASET/PASET Setting */ + 39 00 05 2a 00 00 05 9F + 39 00 05 2b 00 00 0c 2f + /* 4.3 TSP SYNC Setting */ + 39 00 03 f0 5a 5a + 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 + 39 00 03 f0 a5 a5 + /* FD(Fast Discharge) Setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 45 + 15 00 02 b5 48 + 39 00 03 f0 a5 a5 + /* 4.6 FFC Setting (MIPI CLK 529MHz) */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 1E + 39 00 06 c5 09 10 b4 24 fb + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* OSC Spread Setting */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 37 + /* FFC Setting; 0x04 : Disable */ + 39 00 06 c5 04 ff 00 01 64 + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* Dither IP Setting */ + 39 00 03 FC 5A 5A + 15 00 02 b0 86 + 15 00 02 eb 01 + 39 00 03 FC a5 a5 + /* 5 Brightness Control */ + /* 5.1 Dimming Setting */ + 39 10 03 f0 5a 5a + 15 10 02 b0 05 + 15 10 02 b1 01 + 15 10 02 b0 02 + 15 10 02 b5 d3 + 15 10 02 53 20 + 39 10 03 f0 a5 a5 + 39 10 03 51 02 ff + 05 32 01 29 + ]; + + panel-exit-sequence = [ + /* Display off */ + 05 14 01 28 + /* Sleep In */ + 05 00 01 10 + /* VCI stabilization setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 05 + 15 00 02 f4 01 + 39 a0 03 f0 a5 a5 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <280000000>; + hactive = <1140>; + vactive = <3120>; + hfront-porch = <16>; + hsync-len = <8>; + hback-porch = <8>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + &i2c4 { status = "okay"; pinctrl-names = "default"; @@ -211,6 +368,14 @@ }; }; +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + &sdmmc { status = "okay"; }; @@ -237,6 +402,12 @@ }; }; + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + touch { touch_gpio: touch-gpio { rockchip,pins = @@ -262,6 +433,10 @@ }; }; +&pwm13 { + status = "okay"; +}; + &spdif_tx1 { status = "okay"; pinctrl-names = "default"; @@ -315,3 +490,8 @@ &usbhost_dwc3_0 { status = "disabled"; }; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-active-high; +};