diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
index 83abcb124d48..f45731737732 100644
--- a/arch/arm/boot/dts/rv1126.dtsi
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -1234,6 +1234,21 @@
 		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
 			 <&cru CLK_ISP>;
 		clock-names = "aclk_isp", "hclk_isp", "clk_isp";
+		power-domains = <&power RV1126_PD_VI>;
+		iommus = <&rkisp_mmu>;
+		status = "disabled";
+	};
+
+	rkisp_mmu: iommu@ffb51a00 {
+		compatible = "rockchip,iommu";
+		reg = <0xffb51a00 0x100>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_mmu";
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RV1126_PD_VI>;
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
 		status = "disabled";
 	};
 
@@ -1246,6 +1261,23 @@
 		clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
 			 <&cru CLK_ISPP>;
 		clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
+		power-domains = <&power RV1126_PD_ISPP>;
+		iommus = <&rkispp_mmu>;
+		status = "disabled";
+	};
+
+	rkispp_mmu: iommu@ffb60e00 {
+		compatible = "rockchip,iommu";
+		reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1";
+		clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RV1126_PD_ISPP>;
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
 		status = "disabled";
 	};